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multiformat video encoder six 14 - bit noise shaped video dacs data she et ADV7344 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 - 2012 analog devices, inc. all rights reserved . features 74.25 mhz 20 - /30 - bit high definition input support compliant with smpte 274m (1080i), 296m (720p), and 240m (1035i) 6 noise shaped video ? (nsv) 14 - bit video dacs 16 (216 mhz) dac oversampling for sd 8 (216 mhz) dac oversampling for ed 4 (297 mhz) dac oversampling for hd 37 ma maximum dac output current ntsc m, pal b/d/g/h/i/m/n, pal 60 support ntsc and pal square pixel operation (24.54 mhz/29.5 mhz) multiformat video input support 4:2:2 ycrcb (sd, ed, and hd) 4:4:4 ycrcb (ed and hd) 4:4:4 rgb (s d, ed, and hd) multiformat video output support composite (cvbs) and s - video (y - c) component yprpb (sd, ed, and hd) component rgb (sd, ed, and hd) macrovision rev 7.1.l1 (sd) and rev 1.2 (ed) compliant simultaneous sd and ed/hd operation eia/cea - 861b compl iance support copy generation management system (cgms) closed captioning and wide screen signaling (wss) integrated subcarrier locking to external video source complete on - chip video timing generator on - chip test pattern generation on - board voltage reference (optional external input) programmable features luma and chroma filter responses vertical blanking interval (vbi) subcarrier frequency (f sc ) and phase luma delay high definition (hd) programmable features (720p/1080i/1035i) 4 oversampling (297 mhz) int ernal test pattern generator color and black bar, hatch, flat field/frame fully programmable ycrcb to rgb matrix gamma correction programmable adaptive filter control programmable sharpness filter control cgms (720p/1080i) and cgms type b (720p/1080i) dual data rate (ddr) input support enhanced definition (ed) programmable features (525p/625p) 8 oversampling (216 mhz output) internal test pattern generator b lack bar, hatch, flat field/frame individual y and prpb output delay gamma correction programmable adaptive filter control fully programmable ycrcb to rgb matrix undershoot limiter macrovision rev 1.2 (525p/625p) cgms (525p/625p) and cgms type b (525p) dual data rate (ddr) input support standard defin ition (sd) programmable features 16 oversampling (21 6 mhz) internal test pattern generator color and black bar controlled edge rates for start and end of active video individual y and prpb output delay undershoot limiter gamma correction digital noise reduction (dnr) multiple chroma and luma filters luma -s saf filter with programmable gain/attenuation prpb ssaf separate pedestal contro l on component and composite/s -v ideo output vcr ff/rw sync mode macrovision rev 7.1.l1 copy generation management system (cgms) wide screen signaling (wss) closed captioning s erial mpu interface with i 2 c compatibility 3.3 v analog operation 1.8 v digital operation 1.8 v or 3.3 v i/o operation temperature range: ?4 0c to +85 c applications dvd recorders and players high definition blu - ray dvd players
ADV7344 data sheet rev. b | page 2 of 108 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 revision history ............................................................................... 4 general description ......................................................................... 5 functional block diagram .............................................................. 6 specifications ..................................................................................... 7 power supply and voltage specifications .................................. 7 voltage reference specifications ................................................ 7 input clock spec ifications .......................................................... 7 analog output specifications ..................................................... 8 digital input/output specifications 3.3 v ............................. 8 digital input/output specifications 1.8 v ............................. 8 digital timing specifications 3.3 v ........................................ 9 digital timing specifi cations 1.8 v ...................................... 10 mpu port timing specifications ............................................. 11 power specifications .................................................................. 11 video performance specifications ........................................... 12 timing diagrams ............................................................................ 13 absolute maximum ratings .......................................................... 20 thermal resistance .................................................................... 20 esd caution ................................................................................ 20 pin configuration and function descriptions ........................... 21 typical performance characteristics ........................................... 23 mpu port description ................................................................... 28 i 2 c operation .............................................................................. 28 register map access ....................................................................... 30 register programming ............................................................... 30 subaddress regi ster (sr7 to sr0) ............................................ 30 input configuration ....................................................................... 48 standard definition only .......................................................... 48 enhanced definition/high definition only .......................... 50 simultaneous standard definition and enhanced definition/high definition ....................................................... 50 enhanced definition only (at 54 mhz) ................................. 51 output configuration .................................................................... 52 design features ............................................................................... 53 output oversampling ................................................................ 53 hd interlace external p_hsync and p_vsync considerations ............................................................................ 54 ed/hd timing reset ................................................................ 54 sd subcarrier frequency lock, subcarri er phase reset, and timing reset ....................................................................... 54 sd vcr ff/rw sync ................................................................ 54 vertical blanking interval ......................................................... 55 sd subcarrier frequency control ............................................ 55 sd noninterlaced mode ............................................................ 55 sd square pixel mode ............................................................... 55 filters ............................................................................................ 56 ed/hd test pattern color controls ....................................... 57 color space conversion matrix ............................................... 58 sd luma and color scale control ........................................... 59 sd hue adjust control .............................................................. 59 sd brig htness detect ................................................................. 60 sd brightness control ............................................................... 60 sd input standard autodetection ............................................ 60 double buffering ........................................................................ 61 programmable dac gain control .......................................... 61 gamma correction .................................................................... 61 ed/hd sharpness filter and adaptive filter controls ......... 63 ed/hd sharpness filter and adaptive filter application examples ...................................................................................... 64 sd digital noise reduction ...................................................... 65 sd active video edge control ................................................. 67 external horizontal and vertical synchronization control ......................................................................................... 68 low power mode ........................................................................ 69 cable detection .......................................................................... 69 dac autopower - do wn ............................................................. 69 sleep mode .................................................................................. 69 pixel and control port readback ............................................. 69 reset mec hanism ........................................................................ 69 sd teletext insertion ................................................................. 69 printed circuit board layout and design .................................. 71 unused pins ................................................................................ 71 dac configurations .................................................................. 71 voltage reference ....................................................................... 71 video output buffer and optional output filter .................. 71 printed circuit board (pcb) layout ....................................... 72 typical application circuit ....................................................... 74
data sheet ADV7344 rev. b | page 3 of 108 copy generation management system ........................................ 75 sd cgms ..................................................................................... 75 ed cgms ..................................................................................... 75 hd cgms .................................................................................... 75 cgms crc functionality ......................................................... 75 sd wide screen signaling .............................................................. 78 sd closed captioning .................................................................... 79 internal test pattern generation ................................................... 80 sd test p atterns ........................................................................... 80 ed/hd test patterns .................................................................. 80 sd timing ........................................................................................ 81 hd timing ....................................................................................... 86 video output levels ....................................................................... 87 sd yprpb output levels smpte/ebu n10 ........................ 87 ed/hd yprpb output levels ................................................... 88 sd/ed/hd rgb output levels ................................................ 89 sd output plots .......................................................................... 90 video standards .............................................................................. 91 configuration scripts ..................................................................... 93 standard definition .................................................................... 93 enhanced definition .................................................................. 97 high definition ......................................................................... 101 outline dimensions ...................................................................... 105 ordering guide ......................................................................... 105
ADV7344 data sheet rev. b | page 4 of 108 revision history 2/12 rev. a to rev. b change to features section ............................................................. 1 moved revision history section .................................................... 4 changes to table 1 ............................................................................ 5 changes to digital input/output specifications 1.8 v section ..................................................................................... 8 c hanges to table 21 ........................................................................ 34 changes to table 24 ........................................................................ 37 changes to table 29 ........................................................................ 42 changes to 24 - /30 - bit 4:4:4 rgb mode section ........................ 50 deleted ed/hd n onstandard t iming m ode section, figure 58, and table 42, renumbered sequentially ..................................... 54 added external sync polarity section ......................................... 57 c hang ed sd subcarrier frequency lock, subcarrier phase reset, and timing reset section to sd subcarrier frequency lock section .................................................................................... 58 deleted subaddress 0x84, bits[2:1] section, timing reset (tr) mode section, subcarrier phase reset (scr) mode section, and fig ure 59 ................................................................................... 55 deleted figure 60 ............................................................................ 56 changes to ed/hd test patterns section ................................... 87 3/0 9 rev. 0 to rev. a changes to features section ............................................................ 1 deleted detailed features section, changes to table 1 ............... 4 changes to figure 1 .......................................................................... 5 changes to table 6 ............................................................................ 7 added digital input/output spec ifications 1.8 v section and table 7 ................................................................................................ 7 changes to digital timing specifications 3.3 v section and table 8 ................................................................................................ 8 added table 9 .................................................................................... 9 changes to mpu port timing specifications section, default conditions ......................................................................... 10 added power specification s section, default conditions ........ 10 added video performance specif ications, default conditions ....................................................................................... 11 changes to table 13 ........................................................................ 19 changes t o tabl e 15 ........................................................................ 20 changes to mpu port description section ................................ 27 changes to i 2 c operation s ection ............................................... 27 added t able 16 ............................................................................... 27 changes to table 17 ....................................................................... 29 changes to table 18 ....................................................................... 30 cha nges to table 21, 0x30 bit descri ption ................................. 33 changes to ta ble 22, 0x31, bit desc r iption ................................ 34 changes to table 23 ....................................................................... 35 changes to table 29 ....................................................................... 40 changes to table 30 ....................................................................... 41 changes to tabl e 31 ....................................................................... 43 changes to table 32 ....................................................................... 45 added ta ble 33 ............................................................................... 45 added table 34 ............................................................................... 46 changes to sta nda rd definition only section ........................... 47 added figure 52 ................................ ............................................. 49 changes to figure 56 ...................................................................... 50 renamed features section to design features section ............. 52 changes to ed/hd no nstandard timing mode section ......... 52 added hd interlace external p_hsync and p_v sync considerations section .................................................................. 53 changes to sd subcarrier frequency lock, subcarrier phase reset, and timing reset section .................................................. 53 changes to subaddress 0x8c to subaddress 0x8f section ....... 55 changes to programming the f sc section ................................... 55 changes to s ubaddress 0x82, bi t 4 section ................................. 55 added sd manual csc matrix adjust feature section ............ 58 changes to subaddress 0x9c to subaddress 0x9f section ....... 59 changes to sd brightness detect section ................................... 60 changes to figure 70 ...................................................................... 62 added sleep mode section ........................................................... 69 changes to pixel and control port r eadback section .............. 69 added sd teletext insertion section ........................................... 69 added unused pins section .......................................................... 71 a dded figure 85 and figure 8 6 .................................................... 71 changes to po wer supply sequencing section ........................... 73 changes to figure 93 ...................................................................... 76 changes to sd wide screen signaling section .......................... 78 changes to internal te st pattern generation section ............... 80 changes to sd timing, mode 0 (ccir - 656) slave option (subaddress 0x8a = xxxxx000) section .................................. 81 added configuration scripts section .......................................... 93 10/06 revision 0: initial version
data sheet ADV7344 rev. b | page 5 of 108 general description the ADV7344 is a high speed, digital - to - analog video encoder in a 64 - pin lqfp package . six high speed, nsv, 3.3 v, 14- bit video dacs provide support for composite (cvbs), s - video (yc) , and component (yprpb/rgb) an alog outputs in st andard definition (sd) , enhanced definition (ed) , or h igh definition (hd) video formats. the ADV7344 has a 30 - bit pixel input port that can be configured in a variety of ways. sd video formats are supported over a n sdr interface and ed/hd video formats are supported over sdr and ddr interfaces. pixel data ca n be supplied in eith er the ycrcb or rgb color space . the ADV7344 also supports embedded eav/sav timing codes, external video synchronization signals, and i 2 c? communication protocol . in addition, simultaneous sd and ed/hd input and output is supported. f ull - drive dacs ensure that external output buffering is not required , while 216 mhz (sd and ed) and 297 mhz (hd) oversampling ensures that external output filtering is not required . cable detection and dac auto power - down features keep power consumption to a minimum. table 1 lists the video standards directly supported by the ADV7344. table 1 . standards directly supported by the ADV7344 active resolution i/p 1 frame rate (hz) clock input (mhz) standard 72 0 240 p 59.94 27 720 288 p 50 27 720 480 i 29.97 27 itu -r bt. 601/656 720 576 i 25 27 itu -r bt. 601/656 640 480 i 29.97 24.54 ntsc square pixel 768 576 i 25 29.5 pal square pixel 720 483 p 59.94 27 smpte 293m 720 483 p 59.94 27 bta t -1004 720 483 p 59.94 27 itu - r bt.1358 720 576 p 50 27 itu - r bt.1358 720 483 p 59.94 27 itu - r bt.1362 720 576 p 50 27 itu - r bt.1362 1920 1035 i 30 74.25 smpte 240m 1920 1035 i 29.97 74.1758 smpte 240m 1280 720 p 60, 50, 30, 25, 24 74.25 smpte 296m 1280 720 p 23.97, 59.94, 29.97 74.1758 smpte 296m 1920 1080 i 30, 25 74.25 smpte 274m 1920 1080 i 29.97 74.1758 smpte 274m 1920 1080 p 30, 25, 24 74.25 smpte 274m 1920 1080 p 23.98, 29.97 74.1758 smpte 2 74m 1920 1080 p 24 74.25 itu - r bt.709 -5 1 i = interlaced, p = progressive.
ADV7344 data sheet rev. b | page 6 of 108 functional block dia gram r gnd_io v dd_io 8-/10-/16-/20-/ 24-/30-bit sd video data video data s_hsync p_hsync p_vsync p _bl ank s_vsync 14-bit dac 1 dac 1 14-bit dac 2 dac 2 14-bit dac 3 dac 3 14-bit dac 4 dac 4 14-bit dac 5 dac 5 14-bit dac 6 dac 6 multiplexer reference and cable detect 16x/4x oversampling dac pll video timing generator power management control clkin (2) pv dd pgnd ext_lf (2) v ref comp (2) r set (2) sdr/ddr ed/hd input 4:2:2 to 4:4:4 deinterleave p ro grammable hdtv filters sharpness and adaptive filter control ycbcr hdtv test pattern generator g/b rgb async bypass rgb dgnd (2) v dd (2) scl sda alsb sfl mpu port subcarrier frequency lock (sfl) ycrcb to rgb programmable chrominance filter add burst rgb to ycrcb matrix 4:2:2 to 4:4:4 sd deinterleave sin/cos dds block 16 filter 16 filter 4 filter agnd v aa add sync vbi data service insertion programmable luminance filter 06400-001 ADV7344 8-/10-/16-/20-/ 24-/30-bit ed/hd ycbcr to rgb matrix figure 1.
data sheet ADV7344 rev. b | page 7 of 108 specifications power supply and volt age specifications all specifications t min to t max (?40c to +85c), unless otherwise noted. table 2. parameter min typ max unit supply voltages v dd 1.71 1.8 1.89 v v dd_io 1.71 3.3 3.63 v pv dd 1.71 1.8 1.89 v v aa 2.6 3.3 3.465 v power supply rejection ratio 0.002 %/% voltage reference specifications all specifications t min to t max (?40c to +85c), unless otherwise noted. table 3. parameter min typ max unit internal reference range, v ref 1.186 1.248 1.31 v external reference range, v ref 1.15 1.235 1.31 v external v ref current 1 10 a 1 external current required to overdrive internal v ref . input clock specifications v dd = 1.71 v to 1.89 v, pv dd = 1.71 v to 1.89 v, v aa = 2.6 v to 3.465 v, v dd_io = 1.71 v to 3.63 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 4. parameter conditions 1 min typ max unit f clkin_a sd/ed 27 mhz f clkin_a ed (at 54 mhz) 54 mhz f clkin_a hd 74.25 mhz f clkin_b ed 27 mhz f clkin_b hd 74.25 mhz clkin_a high time, t 9 40 % of one clock cycle clkin_a low time, t 10 40 % of one clock cycle clkin_b high time, t 9 40 % of one clock cycle clkin_b low time, t 10 40 % of one clock cycle clkin_a peak-to-peak jitter tolerance 2 ns clkin_b peak-to-peak jitter tolerance 2 ns 1 sd = standard defini tion, ed = enhanced definition (525p/625p), hd = high definition.
ADV7344 data sheet rev. b | page 8 of 108 analog output specifications v dd = 1.71 v to 1.89 v, pv dd = 1.71 v to 1.89 v, v aa = 2.6 v to 3.465 v, v dd_io = 1.71 v to 3.63 v, v ref = 1.235 v (driven externally). all specifications t min to t max (?40c to +85c), unless otherwise noted. table 5. parameter conditions min typ max unit full drive output current (full-scale) r set = 510 , r l = 37.5 33 34.6 37 ma dac 1, dac 2, dac 3 enabled 1 r set = 510 , r l = 37.5 33 33.5 37 ma dac 1 enabled only 2 low-drive output current (full-scale) 3 r set = 4.12 k, r l = 300 4.1 4.3 4.5 ma dac-to-dac matching dac 1 to dac 6 1.0 % output compliance, v oc 0 1.4 v output capacitance, c out dac 1, dac 2, dac 3 10 pf dac 4, dac 5, dac 6 6 pf analog output delay 4 dac 1, dac 2, dac 3 8 ns dac 4, dac 5, dac 6 6 ns dac analog output skew dac 1, dac 2, dac 3 2 ns dac 4, dac 5, dac 6 1 ns 1 applicable to full-drive capable dacs only, that is, dac 1, dac 2, dac 3. 2 the recommended method of bringing this typical value back to the ideal value is by adjusting register 0x0b to the recommended value of 0x12. 3 applicable to all dacs. 4 output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the dac output full-scale t ransition. digital input/output specifications3.3 v v dd = 1.71 v to 1.89 v, pv dd = 1.71 v to 1.89 v, v aa = 2.6 v to 3.465 v, v dd_io = 2.97 v to 3.63 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 6. parameter conditions min typ max unit input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input leakage current, i in v in = v dd_io 10 a input capacitance, c in 4 pf output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current v in = 0.4 v, 2.4 v 1.0 a three-state output capacitance 4 pf digital input/output specifications1.8 v when v dd_io is set to 1.8 v, all the digital video inputs and control inputs, such as i 2 c, hs, and vs, should use 1.8 v levels. v dd = 1.71 v to 1.89 v, pv dd = 1.71 v to 1.89 v, v aa = 2.6 v to 3.465 v, v dd_io = 1.71 v to 1.89 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 7. parameter conditions min typ max unit input high voltage, v ih 0.7 v dd_io v input low voltage, v il 0.3 v dd_io v input capacitance, c in 4 pf output high voltage, v oh i source = 400 a v dd_io C 0.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state output capacitance 4 pf
data sheet ADV7344 rev. b | page 9 of 108 digital timing specifications 3.3 v v dd = 1.71 v to 1.89 v, pv dd = 1.71 v to 1.89 v, v aa = 2.6 v to 3.46 5 v , v dd_io = 2.97 v to 3.63 v. all specifications t min to t max ( ?4 0c to +85c), unless otherwise noted. table 8. parameter conditions 1 min typ max unit video data and video control port 2 , 3 data input setup time, t 11 4 sd 2.1 ns ed/hd -sdr 2.3 ns ed/hd -ddr 2.3 ns ed (at 54 m hz) 1.7 ns data input hold time, t 12 4 sd 1.0 ns ed/hd -sdr 1.1 ns ed/hd -ddr 1.1 ns ed (at 54 mhz) 1.0 ns control input setup time, t 11 4 sd 2.1 ns ed/hd - sdr or ed/hd - ddr 2.3 ns ed (at 54 mhz) 1.7 ns control input hold time, t 12 4 sd 1.0 ns ed/hd - sdr or ed/hd -ddr 1.1 ns ed (at 54 mhz) 1.0 ns control output access time, t 13 4 sd 12 ns e d/hd - sdr, ed/hd - ddr or ed (at 54 mhz) 10 ns control output hold time, t 14 4 sd 4.0 ns ed/hd - sdr, ed/hd - ddr or ed (at 54 mhz) 3.5 ns pipeline delay 5 sd 1 cvbs/yc output s (2) sd oversampling disabled 68 c lock cycles cvbs/yc outputs (16) sd oversampling enabled 67 cl ock cycles component outputs (2) sd oversampling disabled 78 c lock cycles component outputs (16) sd oversampling enabled 84 c lock cycles ed 1 component outputs (1) ed oversampling disabled 41 c lock cycles component outputs (8) ed oversampling enabled 46 c lock cycles hd 1 component outputs (1) hd oversamp ling disabled 40 c lock cycles component outputs (4) hd oversampling enabled 44 c lock cycles 1 sd = standard definition, ed = enhanced definition (525p/625p), hd = high defi nition, sdr = single data rate, ddr = dual data rate. 2 video d ata: c[9:0], y[9:0], and s[9:0]. 3 video c ontrol: p_hsync , p_vsync , p_blank , s_hsync , and s_vsync . 4 gu aranteed by characterization. 5 guaranteed by design.
ADV7344 data sheet rev. b | page 10 of 108 digital timing specifications 1.8 v v dd = 1.71 v to 1.89 v, pv dd = 1.71 v to 1.89 v, v aa = 2.6 v to 3.46 5 v , v dd_io = 1. 71 v to 1. 89 v. all specifications t min to t max ( ?4 0c to +85c), unless otherwise noted. table 9. parameter conditions 1 min typ max unit video data and video control port 2 , 3 data input setup time, t 11 4 sd 1.4 ns ed/hd -sdr 1.9 ns ed/hd -ddr 1.9 ns ed (at 54 mhz) 1.6 ns data input hold time, t 12 4 sd 1.4 ns ed/hd -sdr 1.5 ns ed/hd -ddr 1.5 ns ed (at 54 mhz) 1.3 ns control input setup time, t 11 4 sd 1.4 ns ed/h d - sdr or ed/hd - ddr 1.2 ns ed (at 54 mhz) 1.0 ns control input hold time, t 12 4 sd 1.4 ns ed/hd - sdr or ed/hd -ddr 1.0 ns ed (at 54 mhz) 1.0 ns control output access time, t 13 4 sd 13 ns ed/hd - sdr, ed/hd - ddr or ed (at 54 mhz) 12 ns control output hold time, t 14 4 sd 4.0 ns ed/hd - sdr, ed/hd - ddr or ed (at 54 mhz) 5.0 ns pipeline delay 5 sd 1 cvbs/yc outputs (2) sd oversampling disabled 68 c lock cycles cvbs/yc outputs (16) sd oversampling enabled 67 c lock cycles component outputs (2) sd oversampling disabled 78 c lock cycles component outputs (16) sd oversampling enabled 84 c lock cycles ed 1 component outputs (1) ed oversampling disabled 41 c lock cycles component outputs (8) ed oversampling enabled 46 c lock cycles hd 1 component outputs (1 ) hd oversampling disabled 40 c lock cycles component outputs (4) hd oversampling enabled 44 c lock cycles 1 sd = standard definition, ed = enhanced definition (525p/625p), hd = high definition, sdr = single data rate, ddr = dual data rate. 2 video d ata: c[9:0], y[9:0], and s[9:0]. 3 video c ontrol: p_hsync , p_vsync , p_blank , s_hsync , and s_vsync . 4 guaranteed by characterization. 5 guaranteed by design.
data sheet ADV7344 rev. b | page 11 of 108 mpu port timing specifications v dd = 1.71 v to 1.89 v, pv dd = 1.71 v to 1.89 v, v aa = 2.6 v to 3.465 v, v dd_io = 1.71 v to 3.63 v. all specifications t min to t max (?40c to +85c), unless otherwise noted. table 10. parameter conditions min typ max unit mpu port, i 2 c mode 1 see figure 19 scl frequency 0 400 khz scl high pulse width, t 1 0.6 s scl low pulse width, t 2 1.3 s hold time (start condition), t 3 0.6 s setup time (start condition), t 4 0.6 s data setup time, t 5 100 ns sda, scl rise time, t 6 300 ns sda, scl fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s 1 guaranteed by characterization. power specifications v dd = 1.8 v, pv dd = 1.8 v, v aa = 3.3 v, v dd_io = 3.3 v, t a = 25c. table 11. parameter conditions min typ max unit normal power mode 1, 2 i dd 3 sd only (16 oversampling) 90 ma ed only (8 oversampling) 4 65 ma hd only (4 oversampling) 4 91 ma sd (16 oversampling) and ed (8 oversampling) 95 ma sd (16 oversampling) and hd (4 oversampling) 122 ma i dd_io 1 ma i aa 5 three dacs enabled (ed/hd only) 124 ma six dacs enabled (sd only and simultaneous modes ) 140 ma i pll sd only, ed only, or hd only modes 5 ma simultaneous modes 10 ma sleep mode i dd 5 a i aa 0.3 a i dd_io 0.2 a i pll 0.1 a 1 r set1 = 510 (dac 1, dac 2 and dac 3 operating in full- drive mode). r set2 = 4.12 k (dac 4, dac 5, and dac 6 operating in low drive mode). 2 75% color bar test pattern applied to pixel data pins. 3 i dd is the continuous current required to drive the digital core. 4 applicable to both single data rate (sdr) and dual da ta rate (ddr) input modes. 5 i aa is the total current required to supply all dacs including the v ref circuitry.
ADV7344 data sheet rev. b | page 12 of 108 video performance specifications v dd = 1.8 v, pv dd = 1.8 v, v aa = 3.3 v, v dd_io = 3.3 v, t a = 25c, v ref driven externally. table 12. parameter conditions min typ max unit static performance resolution 14 bits integral nonlinearity r set1 = 510 , r l1 = 37.5 3 lsbs r set2 = 4.12 k, r l2 = 300 4 lsbs differential nonlinearity 1 +ve r set1 = 510 , r l1 = 37.5 1 lsbs r set2 = 4.12 k, r l2 = 300 3.2 lsbs differential nonlinearity 1 ?ve r set1 = 510 , r l1 = 37.5 1.7 lsbs r set2 = 4.12 k, r l2 = 300 1.4 lsbs standard defintion (sd) mode luminance nonlinearity 0.2 % differential gain ntsc 0.2 % differential phase ntsc 0.3 degrees snr luma ramp 64.5 db snr flat field full bandwidth 79.5 db enhanced definition (ed) mode luma bandwidth 12.5 mhz chroma bandwidth 5.8 mhz high definition (hd) mode luma bandwidth 30 mhz chroma bandwidth 13.75 mhz 1 differential nonlinearity (dnl) measures the deviation of the actual dac output voltage step from the ideal. for +ve dnl, the actual step value lies above the ideal step value. for ?ve dnl, the actual step value lies below the ideal step value.
data sheet ADV7344 rev. b | page 13 of 108 timing diagrams the following abbreviations are used in figure 2 to figure 13: ? t 9 = clock high time ? t 10 = clock low time ? t 11 = data setup time ? t 12 = data hold time ? t 13 = control output access time ? t 14 = control output hold time in addition, refer to table 36 for the ADV7344 input configuration. t 9 clkin_a t 10 control outputs s_hsync, s_vsync cr2 cb2 cr0 cb0 *selected by subaddress 0x01, bit 7. in master/slave mode in slave mode y0 y1 y2 s9 to s0/y9 to y0* control inputs t 12 t 11 t 13 t 14 0 6400-002 figure 2. sd only, 8-/10-bit, 4:2:2 ycrcb pixel input mode (input mode 000) in master/slave mode in slave mode clkin_a control outputs s_hsync, s_vsync *selected by subaddress 0x01, bit 7. s9 to s0/y9 to y0* y9 to y0/c9 to c0* control inputs t 9 t 10 cr2 cb2 cr0 cb0 y0 y1 y2 y3 t 12 t 14 t 11 t 13 06400-003 figure 3. sd only, 16-/20-bit, 4:2:2 ycrcb pixel input mode (input mode 000)
ADV7344 data sheet rev. b | page 14 of 108 c9 to c2/c9 to c0 y9 to y2/y9 to y0 control outputs s9 to s2/s9 to s0 t 9 clkin_a t 10 s_hsync, s_vsync control inputs t 11 g0 g1 g2 b0 b1 b2 r0 r1 r2 t 12 t 14 t 13 06400-004 figure 4 . sd only, 24 - /30 - bit, 4:4:4 rgb pixel input mode (input mode 000) y0 y1 y2 y3 y4 y5 y9 to y2/y9 to y0 cr4 cb4 cr2 cb2 cr0 cb0 control outputs clkin_a p_hsync, p_vsync, control inputs p_blank c9 to c2/c9 to c0 t 9 t 10 t 12 t 11 t 14 t 13 06400-005 figure 5 . ed/hd - sdr only, 16 - /20 - bit, 4:2:2 ycrcb pixel input mode (input mod e 001) y0 y1 y2 y3 y4 y5 cr4 cr3 cr2 cr1 cr0 cr5 cb4 cb 3 cb 2 cb1 cb0 cb5 y9 to y2/y9 to y0 control outputs clkin_a p_hsync, p_vsync, control inputs p_blank c9 to c2/c9 to c0 s9 to s2/s9 to s0 t 9 t 10 t 12 t 11 t 14 t 13 06400-006 figure 6 . ed/hd - sdr only, 24 - /30 - bit, 4:4:4 ycrcb pixel input mode (input mode 001)
data sheet ADV7344 rev. b | page 15 of 108 clkin_a c9 to c2/c9 to c0 g0 g1 g2 g3 g4 g5 b0 b1 b2 b3 b4 b5 r0 r1 r2 r3 r4 r5 y9 to y2/y9 to y0 control outputs s9 to s2/s9 to s0 p_hsync, p_vsync, control inputs p_blank t 9 t 10 t 12 t 11 t 14 t 13 06400-007 figure 7 . ed/hd - sdr only, 24 - /30 - bit, 4:4:4 rgb pixel input mode (input mode 001) clkin_a * y9 to y2/y9 to y0 *luma/chromaclock relationship can be inverted using subaddress 0x01, bits 1 and 2. control outputs cr2 y2 cb2 y1 cr0 y0 cb0 t 9 t 10 t 12 t 11 t 12 t 11 t 14 t 13 p_hsync, p_vsync, control inputs p_blank 06400-008 figure 8 . ed/hd - ddr only, 8 - /10 - bit, 4:2:2 ycrcb ( hsync / vsync ) pixel input mode (input mode 010) y1 cr0 y0 cb0 xy 00 00 3ff *luma/chroma clock relationship can be inverted using subaddress 0x01, bits 1 and 2. clkin_a* y9 to y2/y9 to y0 control outputs t 9 t 10 t 12 t 11 t 12 t 11 t 14 t 13 06400-009 figure 9 . ed/hd - ddr only, 8 - /10 - bit, 4:2:2 ycrcb (eav/sav) pixel input mode (input mode 010)
ADV7344 data sheet rev. b | page 16 of 108 t 9 t 10 t 9 t 10 t 11 t 11 y0 y1 y2 y3 y4 y5 ed/hd input sd input s9 to s2/s9 to s0 clkin_a y2 cb2 y1 cr0 y0 cb0 cr4 cb4 cr2 cb2 cr0 cb0 cr2 y6 cb6 c9 to c2/c9 to c0 y9 to y2/y9 to y0 clkin_b p_hsync, p_vsync, control inputs p_blank s_hsync, s_vsync control inputs t 12 t 12 06400-010 figure 10 . sd, ed/hd - sdr input mode, 16 - /20 - bit, 4:2:2 ed/hd and 8 - /10 - bit, sd pixel input mode (input mode 011) cr2 cr2 y2 y1 cr0 ed/hd input sd input cb2 y1 cr0 s9 to s2/s9 to s0 clkin_a y9 to y2/y9 to y0 clkin_b p_hsync, p_vsync, control inputs p_blank s_hsync, s_vsync control inputs t 9 t 10 t 9 t 10 t 12 t 11 t 12 t 11 t 12 t 11 y0 cb0 cb2 cb0 y0 y2 06400-011 figure 11 . sd, ed/hd - ddr input mode, 8 - /10 - bit, 4:2:2 ed/hd and 8 - /10 - bit, sd pixel input mode (input mode 100) clkin_a y9 to y2/y9 to y0 control outputs y1 cr0 y0 cb0 cr2 y2 cb2 p_hsync, p_vsync, control inputs p_blank t 9 t 10 t 12 t 11 t 13 t 14 06400-012 figure 12 . ed only (at 54 mhz), 8 - /10 - bit, 4:2:2 ycrcb ( hsync / vsync ) pixel input mode (input mode 111)
data sheet ADV7344 rev. b | page 17 of 108 t 9 t 11 t 10 t 12 t 13 t 14 clkin_a y9 to y2/y9 to y0 control outputs 3ff 00 00 xy cb0 y0 cr0 y1 06400-013 figure 13 . ed only (at 54 mhz), 8 - /10- bit, 4:2:2 ycrcb (eav/sav) pixel input mode (input mode 111) y0 y1 y2 y3 b a cr2cb 2 cr0cb0 c y output y9 to y2/y9 to y0 c9 to c2/c9 to c0 p_hsync p_vsync p_blank a and b as per relevant standard. c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timing specification section of the data sheet. a falling edge of hsync into the encoder generates a sync falling edge on the output after a time equal to the pipeline delay. 06400-014 figure 14 . ed - sdr, 16 - /20 - bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram
ADV7344 data sheet rev. b | page 18 of 108 y9 to y2/y9 to y0 cb0 y0 cr0 y1 b a a = 32 clock cycles for 525p a = 24 clock cycles for 625p as recommended by standard b(min) = 244 clock cycles for 525p b(min) = 264 clock cycles for 625p p_hsync p_vsync p_blank c y output c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timing specification section of the data sheet. a falling edge of hsync into the encoder generates a sync falling edge on the output after a time equal to the pipeline delay. 06400-015 figure 15 . ed - ddr, 8 - /10 - bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram y0 y1 y2 y3 b a cr2cb 2 cr0cb0 c y output y9 to y2/y9 to y0 c9 to c2/c9 to c0 p_hsync p_vsync p_blank a and b as per relevant standard. c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timing specification section of the data sheet. a falling edge of hsync into the encoder generates a falling edge of tri-level sync on the output after a time equal to the pipeline delay. 06400-016 figure 16 . hd - sdr, 16 - /20 - bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram
data sheet ADV7344 rev. b | page 19 of 108 y9 to y2/y9 to y0 cb0 y0 cr0 y1 b a p_hsync p_vsync p_blank c y output a and b as per relevant standard. c = pipeline delay. please refer to relevant pipeline delay. this can be found in the digital timing specification section of the data sheet. a falling edge of hsync into the encoder generates a falling edge of tri-level sync on the output after a time equal to the pipeline delay. 06400-017 figure 17 . hd - ddr, 8 - /10 - bit, 4:2:2 ycrcb ( hsync / vsync ) input timing diagram cb y cr y pal = 264 clock cycles ntsc = 244 clock cycles s9 to s0/y9 to y0* s_vsync s_hsync *selected by subaddress 0x01, bit 7. 06400-018 figure 18 . sd input timing diagram (timing mod e 1) t 3 t 3 t 4 t 7 t 8 t 5 sda scl t 1 t 2 t 6 06400-019 figure 19 . mpu port timing diagram (i 2 c mode)
ADV7344 data sheet rev. b | page 20 of 108 absolute maximum ratings table 13. parameter 1 rating v aa to agnd ?0.3 v to +3.9 v v dd to dgnd ?0.3 v to +2.3 v pv dd to pgnd ?0.3 v to +2.3 v v dd_io to gnd_io ?0.3 v to +3.9 v agnd to dgnd ?0.3 v to +0.3 v agnd to pgnd ?0.3 v to +0.3 v agnd to gnd_io ?0.3 v to +0.3 v dgnd to pgnd ?0.3 v to +0.3 v dgnd to gnd_io ?0.3 v to +0.3 v pgnd to gnd_io ?0.3 v to +0.3 v digital input voltage to gnd_io ?0.3 v to v dd_io + 0.3 v analog outputs to agnd ?0.3 v to v aa maximum clkin input frequency 80 mhz storage temperature range (t s ) ?65c to +150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec) 260c 1 analog output short circuit to any power supply or common can be of an indefinite duration. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. the ADV7344 is a high performance integrated circuit with an esd rating of <1 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 14. thermal resistance 1 package type ja jc unit 64-lead lqfp 47 11 c/w 1 values are based on a jedec 4-layer test board. the ADV7344 is an rohs-compliant, pb-free product. the lead finish is 100% pure sn electroplate. the device is suitable for pb- free applications up to 255c (5c) ir reflow (jedec std-20). it is backward compatible with conventional snpb soldering processes. the electroplated sn coating can be soldered with sn/pb solder paste at conventional reflow temperatures of 220c to 235c. esd caution
data sheet ADV7344 rev. b | page 21 of 108 pin configuration and function descripti ons 64 gnd_io 63 clkin_b 62 s9 61 s8 60 s7 59 s6 58 s5 57 dgnd 56 v dd 55 s4 54 s3 53 s2 52 s1 51 s0 50 s_hsync 49 s_vsync 47 r set1 46 v ref 45 comp1 42 dac 3 43 dac 2 44 dac 1 48 sfl 41 v aa 40 agnd 39 dac 4 37 dac 6 36 r set2 35 comp2 34 pv dd 33 ext_lf1 38 dac 5 2 y0 3 y1 4 y2 7 y5 6 y4 5 y3 1 v dd_io 8 y6 9 y7 10 v dd 12 y8 13 y9 14 c0 15 c1 16 c2 11 dgnd 17 c3 18 c4 19 alsb 20 sda 21 scl 22 23 p_hsync 24 p_vsync 25 p_blank 26 c6 c5 27 c7 28 c8 29 c9 30 clkin_a 31 32 pgnd pin 1 ADV7344 top view (not to scale) ext_lf2 06400-021 figure 20 . pin configuration table 15 . pin function descriptions pin no. mnemonic input/ output description 13, 12, 9 to 2 y9 to y0 i 10- bit pixel port (y9 to y0). y0 is the lsb. refer to table 36 for input modes. 29 to 25, 18 to 14 c9 to c0 i 10- bit pixel port (c9 to c0). c0 is the lsb. refer to table 36 for input modes. 62 to 58, 55 to 51 s9 to s0 i 10- bit pixel port (s9 to s0). s0 is the lsb. refer to table 36 for input modes. 30 clkin_a i pixel clo ck input for hd only (74.25 mhz), ed 1 only (27 mhz or 54 mhz) , or sd only (27 mhz). 63 clkin_b i pixel clock input for dual modes only. requires a 27 mhz reference clock for ed operation or a 74.25 mhz reference clock for hd operation. 50 s_hsync i/o sd horizontal synchronization signal. this pin can also be configured to output an sd, ed, or hd horizontal synchronization signal. see the external horizontal and vertical synchronization control section. 49 s_vsync i/o sd vertical synchronization signal. this pin can also be configured to output an sd, ed, or hd vertical synchronization signal. see the external horizontal and vertical synchronization control sec tion. 22 p_hsync i ed/hd horizontal synchronization signal. see the external horizontal and vertical synchronization control section. 23 p_vsync i ed/hd vertical synchronization signal. see the external horizontal and vertical synchronization control section. 24 p_blank i ed/hd blanking signal. see the external horizontal and vertical synchronization control section . 48 sfl i/o subcarrier frequency lock (sfl) input. 47 r set1 i this pin is used to control the amplitudes of the dac 1, dac 2, and dac 3 outputs. for full - drive operation (for example, into a 37.5 ? load), a 510 ? resistor must be connected from r set1 to agnd. for low - drive operation (for example, into a 300 ? load), a 4.12 k? resistor must be connected from r set1 to agnd. 36 r set2 i thi s pin is used to control the amplitudes of the dac 4, dac 5, and dac 6 outputs. a 4.12 k? resistor must be connected from r set2 to agnd. 45, 35 comp1, comp2 o compensation pins. connect a 2.2 nf capacitor from both comp pins to v aa . 44, 43, 42 dac 1, da c 2, dac 3 o dac outputs. full - and low - drive capable dacs.
ADV7344 data sheet rev. b | page 22 of 108 pin no. mnemonic input/ output description 39, 38, 37 dac 4, dac 5, dac 6 o dac outputs. low - drive only capable dacs. 21 scl i i 2 c clock input. 20 sda i/o i 2 c data input/output. 19 alsb i this signal sets up the lsb 2 of the mpu i 2 c address (see the power supply sequencing section for more information) . 46 v ref optional external voltage reference input for dacs or voltage reference output. 41 v aa p analog power supply (3.3 v). 10, 56 v dd p digital power supply (1.8 v). for dual - supply configurations, v dd can be connected to other 1.8 v supplies through a ferrite bead or suitable filtering. 1 v dd_io p input/output digital power supply ( 1.8 v or 3.3 v ). 34 pv dd p pll power supply (1.8 v). for dual -s upply configurations, pv dd can be connected to other 1.8 v supplies through a ferrite bead or suitable filtering. 33 ext_lf 1 i extern al loop filter for on - chip pll 1. 31 ext_lf 2 i external loop filter for on - chip pll 2. 32 pgnd g pll ground pin. 40 agn d g analog ground pin. 11, 57 dgnd g digital ground pin. 64 gnd_io g input/output supply ground pin. 1 ed = enhanced definition = 525p and 625p. 2 lsb = least significant bit. in the ADV7344, setting the lsb to 0 sets the i 2 c address to 0xd4. setting it to 1 sets the i 2 c address to 0 xd6.
data sheet ADV7344 rev. b | page 23 of 108 typical performance characteristics frequency (mhz) ed pr/pb response. linear interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 06400-022 figure 21 . ed 8 oversampling, prpb filter (linear) response frequency (mhz) ed pr/pb response. ssaf interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 06400-023 figure 22 . ed 8 oversampling, prpb filter (ssaf ? ) response frequency (mhz) y response in ed 8 oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 06400-024 figure 23 . ed 8 oversampling, y filter response frequency (mhz) y response in ed 8 oversampling mode gain (db) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?3.0 12 2 4 6 8 10 0 06400-025 figure 24 . ed 8 oversampling, y filter response (focus on pass band) frequency (mhz) hd pr/pb response. ssaf interp from 4:2:2 to 4:4:4 10 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?100 ?80 ?90 148. 0 18. 5 37.0 55.5 74.0 92.5 111.0 129.5 0 06400-026 figure 25 . hd 4 oversampling, prpb (ssaf) filter response (4:2:2 input) hd pr/pb response. 4:4:4 input mode gain (db) frequency (mhz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 20 30 40 50 60 70 80 90 100 110 120 130 140 06400-027 figure 26 . hd 4 oversampling, prpb (ssaf) filter response (4:4:4 input)
ADV7344 data sheet rev. b | page 24 of 108 frequency (mhz) y response in hd 4 oversampling mode 10 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?100 ?80 ?90 148.0 18.5 37.0 55.5 74.0 92.5 111.0 129.5 0 06400-028 figure 27 . hd 4 oversampling, y filter response y pass band in hd 4x oversampling mode 3.0 ?12.0 27.750 46.250 frequency (mhz) gain (db) 1.5 0 ?1.5 ?3.0 ?4.5 ?6.0 ?7. 5 ?9.0 ?10.5 30.063 32.375 34.688 37.000 39.312 41.625 43.937 06400-029 figure 28 . hd 4 oversampling, y filter response (focus on pass band) frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06400-030 figure 29 . sd ntsc, luma low - pass filter response frequenc y (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06400-031 figure 30 . sd pal, luma low - pass filter response frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06400-032 figure 31 . sd ntsc, luma notch filter response frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06400-033 figure 32 . sd pal, luma notch filter response
data sheet ADV7344 rev. b | page 25 of 108 frequency (mhz) y response in sd oversampling mode gain (db) 0 ?50 ?80 0 20 40 60 80 100 120 140 160 180 200 ?10 ?40 ?60 ?70 ?20 ?30 06400-034 figure 33 . sd, 16 oversampling, y filter response frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 06400-035 figur e 34 . sd luma ssaf filter response up to 12 mhz frequency (mhz) 4 7 magnitude (db) 2 ?2 ?6 ?8 ?12 0 ?4 5 ?10 6 0 1 2 3 4 06400-036 figure 35 . sd luma ssaf filter, programmable responses frequency (mhz) 7 magnitude (db) 5 4 2 1 ?1 3 5 0 6 0 1 2 3 4 06400-037 figure 36 . sd luma ssaf filter, programmable gain frequency (mhz) 7 magnitude (db) 1 0 ?2 ?3 ?5 ?1 5 ?4 6 0 1 2 3 4 06400-038 figure 37 . sd luma ssaf filter, programmable attenuation frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-039 figure 38 . sd luma cif low - pass filter response
ADV7344 data sheet rev. b | page 26 of 108 frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-040 figure 39 . sd luma qcif low - pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-041 figure 40 . sd chroma 3.0 mhz low - pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-042 figure 41 . sd chroma 2.0 mhz low - pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-043 figure 42 . sd chroma 1.3 mhz low - pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-044 figure 43 . sd chroma 1.0 mhz low - pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-045 figure 44 . sd chroma 0.65 mhz low - pass filter response
data sheet ADV7344 rev. b | page 27 of 108 frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-046 figure 45 . sd chroma cif low - pass filter response frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 06400-047 figure 46 . sd chroma qcif low - pass filter response
ADV7344 data sheet rev. b | page 28 of 108 mpu port description devices such as a microprocessor can communicate with the ADV7344 through a 2 - wire serial l(i 2 c- compatible) bus. after power - up or reset, the mpu port is configured for i 2 c operation. i 2 c operation the a dv7344 supports a 2 - wire serial (i 2 c- compatible) microprocessor bus driving multiple peripherals. this port operates in an open - drain configuration. two wires , serial data (sda) and serial clock (scl), carry information between any device connected to the bus and the ADV7344. the slave add ress of the ADV7344 depend s on the operation (read or write) and the state of the alsb pin (0 or 1). see table 16 and figure 47. the lsb sets either a read or a write oper ation . logic 1 corresponds to a read operation, and logic 0 corresponds to a write operation. a1 is controlled by setting the alsb pin of the ADV7344 to logic 0 or logic 1. table 16. ADV7344 i 2 c slave addresses device alsb operatio n slave address ADV7344 0 write 0xd4 0 read 0xd5 1 write 0xd6 1 read 0xd7 1 1 0 1 0 1 a1 x address control set up by alsb read/write control 0 write 1 read 06400-048 figure 47 . adv7 344 i 2 c slave address analog devices, inc., strongly recommends tying alsb to v dd_io . if this is not done, a power supply sequence (pss) may be required . for more information on the pss, see the power supply sequencing s ection . the various devices on the bus use the following protocol. the master initiates a data transfer by establishing a start condition, de fined by a high - to - low transition on sda while scl remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (7 - bit address plus the r/ w bit).the bi ts are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point a nd maintain an idle condition. the idle condition occurs when the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master writes information to the peripheral. logic 1 on the lsb of the first byte means that the master reads information from the peripheral. the ADV7344 acts as a standard slave device on the bus. the data on the sda pin is eight bits long, supporting the 7 - bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. there is a subaddress auto - increment facility. this allo ws data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one - by - one basis witho ut updating all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. duri ng a given scl high period, the user should issue only a start condition, a stop condition, or a stop condition followed by a start condition. if an invalid subaddress is issued by the user, the ADV7344 does no t issue an acknowledge but return s to the id le condition. if the user uses the auto - increment method of addressing the encoder and exceeds the highest subaddress, the following actions are taken: ? in read mode, the highest subaddress register contents are output until the master device issues a no ack nowledge. this indicates the end of a read. a no acknowledge condition occurs when the sda line is not pulled low on the ninth pulse. ? in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7344, and the part returns to the idle condition. figure 48 shows an example of data transfer for a write sequence and the start and stop conditions. figure 49 shows bus write and read sequence s.
data sheet ADV7344 rev. b | page 29 of 108 sda scl start addr r/ w ack subaddress ack data ack stop 1?7 8 9 s 1?7 1?7 p 8 9 8 9 06400-049 figure 48 . i 2 c data transfer write sequence read sequence s slave addr a(s) subaddr a(s) data data a(s) p s slave addr a(s) subaddr a(s) s slave addr a(s) data dat a a(m) a(m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master lsb = 0 lsb = 1 a(s) 06400-050 figure 49 . i 2 c read and write sequence
ADV7344 data sheet rev. b | page 30 of 108 register map access a microprocessor can read from or write to all registers of the ADV7344 via the mpu port, except for reg isters that are specified as read - only or write - only registers. the subaddress register determines which register the next read or write operation accesses. all communication through the mpu port starts with an access to the subaddress register. a read/ write operation is then performed from/to the target address, which increments to the next address until the transaction is complete. register programming table 17 to tabl e 35 describe the functionality of each register. all registers can be read from as well as written to, unless otherwise stated. subaddress register (sr7 to sr0) the subaddress register is an 8 - bit write - only register. after the mpu port is accessed and a read/write operation is sele cted, the subaddress is set up. the subaddress register determines to or from which register the operation takes place. table 17 . register 0x00 sr7 to bit number register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0x00 power m ode sleep m ode. with this control enabled, the current consumption is reduced to a level. all dacs and the internal pll circuit s are disabled. r egisters can be read from and written to in sleep mode. 0 sleep mod e off 0x12 1 sleep mode on pll and o versampling c ontrol. this control allows the internal pll 1 circuit to be powered down and the oversampling to be switched off. 0 pll 1 on 1 pll 1 off dac 3: power o n/ off. 0 dac 3 off 1 dac 3 on dac 2: p o wer o n/ off. 0 dac 2 off 1 dac 2 on dac 1: power o n/ off. 0 dac 1 off 1 dac 1 on dac 6: power o n/ off. 0 dac 6 off 1 dac 6 on dac 5: power o n/ off. 0 dac 5 off 1 dac 5 on dac 4: power o n/ off. 0 dac 4 off 1 dac 4 on
data sheet ADV7344 rev. b | page 31 of 108 table 18 . register 0x01 to register 0x09 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x01 mode s elect reserved. 0 0x00 ddr c lock e dge a lign - ment (on ly used for ed - 2 and hd - ddr modes ) 0 0 chroma clocked in on rising clock edge; luma clocked in on falling clock edge . 0 1 reserved . 1 0 reserved . 1 1 luma clocked in on rising clock edge ; chroma clocked in on falling clock edge . reserved 0 input mode (see subaddress 0x30 , bits [7:3] for ed/hd standard selection ) 0 0 0 sd input only . 0 0 1 ed/hd - sdr input only . 0 1 0 ed/hd - ddr input only . 0 1 1 sd and ed/hd - sdr . 1 0 0 sd and ed/hd - dd r. 1 0 1 reserved . 1 1 0 reserved . 1 1 1 ed only (at 54 mhz) . y/c/s bus s wap 0 allows data to be applied to data ports in various c onfigurations (sd feature only) . 1 0x02 mode register 0 reserved 0 0 must be written to this bit . 0x20 hd i nterlace e xternal vsync and hsync 0 default . 1 if using hd hsync / vsync interlace mode, setting this bit to 1 is recommended (see the hd interlace external p_hsync and p_vsync considerations section for more information) . test p attern black b ar 3 0 disabled . 1 enabled . manual csc m atrix a djust 0 disable manual csc matrix adjust . 1 enable manual csc matrix adjust . sync on rgb. 0 no sync . 1 sync on all rgb outputs . rgb/yprpb o utput s elect 0 rgb component outputs . 1 yprpb component outputs . sd s ync o utput e nable 0 no sync output . 1 output sd sy ncs on hsync and vsync pins . ed/hd s ync output e nable 0 no sync output . 1 output ed/hd syncs on hsync and vsync pins . 0x03 ed/hd csc ma trix 0 x x lsbs for gy . 0x03 0x04 ed/hd csc matrix 1 x x lsbs for rv . 0xf0 x x lsbs for bu . x x lsbs for gv . x x lsbs for gu . 0x05 ed/hd csc matrix 2 x x x x x x x x bits[9:2 ] for g y. 0x4e 0x06 ed/hd csc matrix 3 x x x x x x x x bits[9:2] for gu . 0x0e 0x07 ed/hd csc matrix 4 x x x x x x x x bits[9:2] for gv . 0x24 0x08 ed/hd csc matrix 5 x x x x x x x x bits[9:2] for bu . 0x92 0x09 ed/hd csc ma trix 6 x x x x x x x x bits[9:2] for rv . 0x7c 1 x = logic 0 or logic 1. 2 ed = enhanced definition = 525p and 625p. 3 subaddress 0x31, bit 2 must also be enabled (ed/hd). subaddress 0x84, bit 6 must also be enabled (sd).
ADV7344 data sheet rev. b | page 32 of 108 table 19 . register 0x0a to register 0x1 0 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x0a dac 4, dac 5, dac 6 o utput l evel s positive g ain to dac output voltage 0 0 0 0 0 0 0 0 0% 0x00 0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 +0.036% 0 0 1 1 1 1 1 1 +7.382% 0 1 0 0 0 0 0 0 + 7.5% negative g ain to dac output voltage 1 1 0 0 0 0 0 0 ?7.5% 1 1 0 0 0 0 0 1 ?7.382% 1 0 0 0 0 0 1 0 ?7.364% 1 1 1 1 1 1 1 1 ?0.018% 0x0b dac 1, dac 2, dac 3 o utput l evel s positive g ain to dac output voltage 0 0 0 0 0 0 0 0 0% 0x00 0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 +0.036% 0 0 1 1 1 1 1 1 +7.382% 0 1 0 0 0 0 0 0 +7.5% negative g ain to dac output voltage 1 1 0 0 0 0 0 0 ?7.5% 1 1 0 0 0 0 0 1 ?7.382% 1 0 0 0 0 0 1 0 ?7.364% 1 1 1 1 1 1 1 1 ?0.018% 0x0d dac p ower m ode dac 1 low power enable 0 dac 1 low power disabled 0x00 1 dac 1 low power enabled dac 2 low power enable 0 dac 2 low power disabled 1 dac 2 low power enabled dac 3 low power enable 0 dac 3 low power disabled 1 dac 3 low power enabled reserved 0 0 0 0 0 0x10 cable d etection da c 1 c able detect (read o nly) 0 cable detected on dac 1 0x00 1 dac 1 unconnected dac 2 c able detect (read o nly) 0 cable detected on dac 2 1 dac 2 unconnected reserved 0 0 unconnected dac a utopowe r- down 0 dac auto power - down disable 1 dac auto power - down enable reserved 0 0 0
data sheet ADV7344 rev. b | page 33 of 10 8 table 20 . register 0x12 to register 0x1 7 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 registe r setting value 0x12 pixel port r eadback ( s b us msbs ) s[9:2] r eadback x x x x x x x x read only . 0x xx 0x13 pixel port r eadback ( y b us msbs ) y[9:2] r eadback x x x x x x x x read only . 0xxx 0x14 pixel port readback (c b us msbs) c[9:2] r eadback x x x x x x x x read only . 0xxx 0x15 pixel port readback (s, y, and c b us lsbs) c[1:0] r eadback x x read only . 0x xx y[1:0] readback x x s[1:0] readback x x reserved 0 0 0x16 control port r eadback p_blank x read only . 0xxx p_ vsync x p_ h sync x s_ vsync x s_ hsync x sfl x reserved 0 0 0x17 software r eset reserved 0 0x00 software r eset 0 writing a 1 resets the device; this is a self - clearing bit . 1 reserved 0 0 0 0 0 0 1 x = logic 0 or logic 1.
ADV7344 data sheet rev. b | page 34 of 108 table 21 . register 0x30 sr7 to bit number reset sr0 register bit descr iption 7 6 5 4 3 2 1 0 register setting note value 0x30 ed/hd mode register 1 ed/hd output standard. 0 0 eia770.2 output eia770.3 output ed hd 0x00 0 1 eia770.1 output . 1 0 outp ut levels for full input range. 1 1 reserved ed/hd input s ynchronization f ormat 0 external hsync , vsync and field inputs 1 1 embedded eav/sav codes ed/hd s tandard 2 0 0 0 0 0 smpte 293m,, itu - bt.135 8 525p at 59.94 hz 0 0 0 1 0 bta- 1004, itu - bt.1362 525p at 59.94 hz 0 0 0 1 1 itu- bt.1358 625p at 50 hz 0 0 1 0 0 itu- bt.1362 625p at 50 hz 0 0 1 0 1 smpte 296m - 1, smpte 274m -2 720p at 60/59.94 hz 0 0 1 1 0 smpte 2 96m -3 720p at 50 hz 0 0 1 1 1 smpte 296m - 4, smpte 274m -5 720p at 30/29.97 hz 0 1 0 0 0 smpte 296m -6 720p at 25 hz 0 1 0 0 1 smpte 296m - 7, smpte 29 6m -8 720p at 24/23.98 hz 0 1 0 1 0 smpte 240m 1035i at 60/59.94 hz 0 1 0 1 1 reserved 0 1 1 0 0 reserved 0 1 1 0 1 smpte 274m - 4, smpte 274m -5 1080i at 30/29.97 hz 0 1 1 1 0 smpte 274m - 6 1080i at 25 hz 0 1 1 1 1 smpte 274m - 7, smpte 274m -8 1080p at 3 0/29.97 hz 1 0 0 0 0 smpte 274m -9 1080p at 25 hz 1 0 0 0 1 smpte 274m - 10, smpte 274m - 11 1080p at 2 4/23.98 hz 1 0 0 1 0 itu- r bt.709 - 1080psf at 24 hz 10011 C 11111 reserved 1 synchronization can be controlled with a combin ation of either hsync and vsync inputs or hsync and field inputs , depending on subaddress 0x34, bit 6. 2 see the hd interlace external p_hsync and p_vsync considerations section for more information.
data sheet ADV7344 rev. b | page 35 of 108 table 22 . register 0x31 to register 0x33 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x31 ed/hd mode register 2 ed/hd pixel da ta v alid 0 pixel data valid off 0x00 1 pixel data valid on reserved 0 ed/hd t est p attern e nab le 0 hd test pattern off 1 hd test pattern on ed/hd test pattern hatch/field 0 hatch 1 field/frame ed/hd vbi o pen 0 disabled 1 enabled ed /hd undershoot l imiter 0 0 disabled 0 1 ?11 ire 1 0 ?6 ire 1 1 ?1.5 ire ed/hd sharpness f ilter 0 disabled 1 enabled 0x32 ed/hd mode register 3 ed/hd y delay with r espect to the falling e dge of hsync 0 0 0 0 clock cycl es 0x00 0 0 1 1 clock cycle 0 1 0 2 clock cycles 0 1 1 3 clock cycles 1 0 0 4 clock cycles ed/hd c olor d elay with r espect to the falling edge of hsync 0 0 0 0 clock cycle s 0 0 1 1 clock cycle 0 1 0 2 clock cycles 0 1 1 3 clock cycles 1 0 0 4 clock cycles ed/hd cgms 0 disabled 1 enabled ed/hd cgms crc 0 disabled 1 enabled 0x33 ed/hd mode register 4 ed/hd cr/cb sequence 0 cb after falling edge of hsync 0x68 1 cr after falling edge of hsync reserved 0 0 must be written to this bit ed/hd input format 0 8- bit input 1 10- bit input sinc c ompensation f ilter on dac 1, dac 2, dac 3 0 disabled 1 enabled reserved 0 0 must be written to this bit ed/hd chroma ssaf 0 disabled 1 enabled ed/hd chroma input 0 4:4:4 1 4:2:2 ed/hd double buffering 0 disabled 1 enabled
ADV7344 data sheet rev. b | page 36 of 108 table 23 . register 0x34 to register 0x35 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x34 ed/hd mode register 5 ed/hd t iming r eset 0 interna l ed/hd timing counters enabled 0x48 1 resets the internal ed/hd timing counters ed/hd hsync control 1 0 hsync output control (refer to table 56 ) 1 ed/hd vsync control 1 0 vsync output co ntrol (refer to table 57 ) 1 ed/hd blank polarity 0 p_blank active high 1 p_blank active low ed macrovision ? enable 0 macrovision disabled 1 macrovision enabled reserved 0 0 must be written to this bit ed/hd vsync /field input 0 0 = field input 1 1 = vsync input horizontal/ vertical c ounters 2 0 update field/line counter 1 field/line counter free running 0x35 ed/hd mode register 6 reserved 0 0x00 ed/hd rgb input enable 0 disabled 1 enabled ed/hd s ync on prpb 0 disabled 1 enabled ed/hd color dac swap 0 dac 2 = pb, dac 3 = pr 1 dac 2 = pr, dac 3 = pb ed/h d gamma correction curve select 0 gamma c orrection curve a 1 gamma c orrection curve b ed/hd g amma correction enabl e 0 disabled 1 enabled ed/hd a daptive filter m ode 0 mode a 1 mode b ed/hd a daptive filter e nable 0 disabled 1 enabled 1 used in conjunction with ed/hd s ync output enable in subaddress 0x02, bit 7 = 1. 2 when set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the select ed standard. when set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
data sheet ADV7344 rev. b | page 37 of 108 table 24 . register 0x36 to register 0x43 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x36 ed/hd y l evel 2 ed/hd test pattern y l evel x x x x x x x x y level value 0xa0 0x37 ed/hd cr l evel 2 ed/hd test pattern cr l evel x x x x x x x x cr level value 0x80 0x38 ed/hd cb l evel 2 ed/hd test pattern cb l evel x x x x x x x x cb level value 0x80 0x39 ed/hd mode register 7 reserved 0 0 0 0 0 0x00 ed/hd eia/cea - 861b synchronization compliance 0 disabled 1 enabled reserved 0 0 0x3a ed/hd mode register 8 inv_phsync_pol 0 disabled 0x00 1 enabled inv_pvsync_pol 0 disabled 1 enabled inv_pblank_pol 0 disabled 1 enabled reserved 0 0 0 0 0 0x40 ed/hd sharpness filter g ain ed/hd sharpness filter g ain, value a 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 1 1 1 1 gain a = ?1 ed/hd sharpness filter g ain , value b 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 1 1 1 1 gain b = ?1 0x41 ed/hd cgms data 0 ed/hd cgms data bits 0 0 0 0 c19 c18 c17 c16 cgms c19 to c16 0x00 0x42 ed/hd cgms data 1 ed/hd cgms data bits c15 c14 c13 c12 c11 c10 c9 c8 cgms c15 to c8 0x00 0x43 ed/hd cgms data 2 ed/hd cgms data bits c7 c6 c5 c4 c3 c2 c1 c0 cgms c7 to c0 0x00 1 x = logic 0 or logic 1. 2 for use with ed/hd internal test patterns only (subaddress 0x31, bit 2 = 1). table 25 . register 0x44 to register 0x57 sr7 to bit number 1 register re set sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0x44 ed/hd gamma a0 ed/hd gamma curve a (point 24) x x x x x x x x a0 0x00 0x45 ed/hd gamma a1 ed/hd gamma curve a (point 32) x x x x x x x x a1 0x00 0x46 ed/h d gamma a2 ed/hd gamma curve a (point 48) x x x x x x x x a2 0x00 0x47 ed/hd gamma a3 ed/hd gamma curve a (point 64) x x x x x x x x a3 0x00 0x48 ed/hd gamma a4 ed/hd gamma curve a (point 80) x x x x x x x x a4 0x00 0x49 ed/hd gamma a5 ed/hd gamma curve a (point 96) x x x x x x x x a5 0x00 0x4a ed/hd gamma a6 ed/hd gamma curve a (point 128) x x x x x x x x a6 0x00 0x4b ed/hd gamma a7 ed/hd gamma curve a (point 160) x x x x x x x x a7 0x00 0x4c ed/h d gamma a8 ed/hd gamma curve a (point 192) x x x x x x x x a8 0x00 0x4d ed/hd gamma a9 ed/hd gamma curve a (point 224) x x x x x x x x a9 0x00 0x4e ed/hd gamma b0 ed/hd gamma curve b (point 24) x x x x x x x x b0 0x00 0x4f ed/ hd gamma b1 ed/hd gamma curve b (point 32) x x x x x x x x b1 0x00 0x50 ed/hd gamma b2 ed/hd gamma curve b (point 48) x x x x x x x x b2 0x00
ADV7344 data sheet rev. b | page 38 of 108 sr7 to bit number 1 register re set sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0x51 ed/hd gamma b3 ed/hd gamma curve b (point 64) x x x x x x x x b3 0x00 0x52 ed/h d gamma b4 ed/hd gamma curve b (point 80) x x x x x x x x b4 0x00 0x53 ed/hd gamma b5 ed/hd gamma curve b (point 96) x x x x x x x x b5 0x00 0x54 ed/hd gamma b6 ed/hd gamma curve b (point 128) x x x x x x x x b6 0x00 0x55 ed/h d gamma b7 ed/hd gamma curve b (point 160) x x x x x x x x b7 0x00 0x56 ed/hd gamma b8 ed/hd gamma curve b (point 192) x x x x x x x x b8 0x00 0x57 ed/hd gamma b9 ed/hd gamma curve b (point 224) x x x x x x x x b9 0x00 1 x = logic 0 or logic 1. table 26 . register 0x58 to register 0x5d sr7 to bit number 1 register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0x58 ed/hd adaptive filter gain 1 ed/hd adaptive filter gain 1, value a 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 1 1 1 1 gain a = ?1 ed/hd adaptive filter gain 1, value b 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 1 1 1 1 gain b = ?1 0x59 ed/hd adaptive filter gain 2 ed/hd adaptive filter gain 2, value a 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 1 1 1 1 gain a = ?1 ed/hd adaptive filter gain 2, value b 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 1 1 1 1 gain b = ?1 0x5a ed/hd adaptive filter gain 3 ed/hd adaptive filter gain 3, value a 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 1 1 1 1 gain a = ?1 ed/hd adaptive filter gain 3, value b 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 1 1 1 1 gain b = ?1
data sheet ADV7344 rev. b | page 39 of 108 sr7 to bit number 1 register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0x5b ed/hd adaptive filter threshold a ed/ hd adaptive filter threshold a x x x x x x x x threshold a 0x00 0x5c ed/hd adaptive filter threshold b ed/ hd adaptiv e filter threshold b x x x x x x x x threshold b 0x00 0x5d ed/hd adaptive filter threshold c ed/ hd adaptive filter threshold c x x x x x x x x threshold c 0x00 1 x = logic 0 or logic 1. table 27 . register 0x5e to register 0x6e sr7 to bit number register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0x5e ed/hd cgms type b register 0 ed/hd cgms type b e nable 0 disabled 0x00 1 enabled ed/hd cgms type b crc e nable 0 disabled 1 enabled ed/hd cgms type b h eader b its h5 h4 h3 h2 h1 h0 h5 to h0 0x5f ed/hd cgms type b register 1 ed/hd cgms type b d ata b its. p7 p6 p5 p4 p3 p2 p1 p0 p7 to p0 0x00 0x60 ed/hd cgms type b register 2 ed/hd cgms type b data b its p15 p14 p13 p12 p11 p10 p9 p8 p15 to p8 0x00 0x61 ed/hd cgms type b register 3 ed/hd cgms type b d ata b its p23 p22 p21 p20 p19 p18 p17 p16 p23 to p16 0x00 0x62 ed/hd cgms type b register 4 ed/hd cgms type b d ata b its p31 p30 p29 p28 p27 p26 p25 p24 p31 to p24 0x00 0x63 ed/hd cgms type b register 5 ed/hd cgms type b d ata b its p39 p38 p37 p36 p35 p34 p33 p32 p39 to p32 0x00 0x64 ed/hd cgms type b register 6 ed/hd cgms type b d ata b its p47 p46 p45 p44 p43 p42 p41 p40 p47 to p40 0x00 0x65 ed/hd cgms type b registe r 7 ed/hd cgms type b d ata b its p55 p54 p53 p52 p51 p50 p49 p48 p55 to p48 0x00 0x66 ed/hd cgms type b register 8 ed/hd cgms type b d ata b its p63 p62 p61 p60 p59 p58 p57 p56 p63 to p56 0x00 0x67 ed/hd cgms type b register 9 ed/hd cgms type b d ata b its p7 1 p70 p69 p68 p67 p66 p65 p64 p71 to p64 0x00 0x68 ed/hd cgms type b register 10 ed/hd cgms type b d ata b its p79 p78 p77 p76 p75 p74 p73 p72 p79 to p72 0x00 0x69 ed/hd cgms type b register 11 ed/hd cgms type b d ata b its p87 p86 p85 p84 p83 p82 p81 p80 p8 7 to p80 0x00 0x6a ed/hd cgms type b register 12 ed/hd cgms type b d ata b its p95 p94 p93 p92 p91 p90 p89 p88 p95 to p88 0x00 0x6b ed/hd cgms type b register 13 ed/hd cgms type b d ata b its p103 p102 p101 p100 p99 p98 p97 p96 p103 to p96 0x00 0x6c ed/hd c gms type b register 14 ed/hd cgms type b d ata b its p111 p110 p109 p108 p107 p106 p105 p104 p111 to p104 0x00 0x6d ed/hd cgms type b register 15 ed/hd cgms type b d ata b its p119 p118 p117 p116 p115 p114 p113 p112 p119 to p112 0x00 0x6e ed/hd cgms type b r egister 16 ed/hd cgms type b d ata b its p127 p126 p125 p124 p123 p122 p121 p120 p127 to p120 0x00
ADV7344 data sheet rev. b | page 40 of 108 table 28 . register 0x80 to register 0x83 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x80 sd mode register 1 sd standard 0 0 ntsc 0x10 0 1 pal b/d/g/h/i 1 0 pal m 1 1 pal n sd luma filter 0 0 0 lpf ntsc 0 0 1 lpf pal 0 1 0 notch ntsc 0 1 1 notch pal 1 0 0 ssaf luma 1 0 1 luma cif 1 1 0 luma qcif 1 1 1 reserved sd chroma filter 0 0 0 1.3 mhz 0 0 1 0.65 mhz 0 1 0 1.0 mhz 0 1 1 2 .0 mhz 1 0 0 reserved 1 0 1 chroma cif 1 1 0 chroma qcif 1 1 1 3.0 mhz 0x82 sd mode register 2 sd prpb ssaf 0 disabled 0x0b 1 enabled sd dac output 1 0 refer to table 37 1 sd dac output 2 0 refer to table 37 1 sd pedestal 0 disabled 1 enabled sd square pixel mode 0 disabled 1 enabled sd vcr ff/rw sync 0 disabled 1 enabled sd pixel data valid 0 disabled 1 enabled sd active video edge control 0 disabled 1 enabled 0x83 sd mode register 3 sd p edestal on yprpb output 0 no pedestal on y prpb 0x04 1 7.5 ire pedestal on y prpb sd output levels y 0 y = 700 mv/300 mv 1 y = 714 mv/286 mv sd output levels prpb 0 0 700 m v p - p (pal), 1000 mv p - p (ntsc) 0 1 700 mv p -p 1 0 1000 mv p -p 1 1 648 mv p -p sd vbi open 0 disabled 1 enabled sd c l osed captioning field control 0 0 closed captioning disabled 0 1 closed captioning on odd field only 1 0 closed captioning on even field only 1 1 cl osed captioning on both fields reserved 0 reserved
data sheet ADV7344 rev. b | page 41 of 108 table 29 . register 0x84 to register 0x89 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x84 sd mode register 4 reserved 0 0x 00 sd sfl/scr/t r mode select 0 0 disabled . 1 1 sfl mode enabled . sd active video length 0 720 pixels . 1 710 (ntsc), 702 (pal) . sd chroma 0 chroma enabled . 1 chroma disabled . sd burst 0 enabled . 1 disabled. sd color bars 0 disabled . 1 enabled . sd luma/chroma swap 0 dac 2 = luma, dac 3 = chroma . 1 dac 2 = chroma, dac 3 = luma. 0x86 sd mode register 5 ntsc color subcarrier adjust (d elay from the falling edge of the output hsync pulse to the start of color burst) 0 0 5.1 7 s. 0x02 0 1 5.31 s. 1 0 5.59 s (must be set for macrovision compliance) . 1 1 reserved . reserved 0 sd eia/cea - 861b synchronization compliance 0 disabled . 1 enabled . reserved 0 0 sd horizontal/vertical counter m ode 1 0 update field/line counter . 1 field/line counter free running . sd rgb color swap 0 normal . 1 color reversal enabled . 0x87 sd mode register 6 sd luma and color scale c on trol 0 disabled . 0x00 1 enabled . sd luma scale saturation 0 disabled . 1 enabled . sd hue adjust 0 disabled . 1 enabled. sd brightness 0 disabled. 1 enabled. sd luma ssaf gain 0 disabled. 1 enabled. sd input standard a utod etect 0 disabled. 1 enabled . reserved. 0 0 must be written to this bit . sd rgb input enable 0 sd ycrcb input . 1 sd rgb input .
ADV7344 data sheet rev. b | page 42 of 108 sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x88 sd mode register 7 reserved 0 0x00 sd n oninterlaced m ode 0 disabled . 1 enabled. sd double buffering 0 disabled . 1 enabled . sd i nput f ormat 0 0 8- bit ycbcr input. 0 1 16- bit ycbcr input. 1 0 10- bit ycbcr input /16 - /24 - /30 - bit rgb input . 1 1 20- bit ycbcr input. sd digital noise reduction 0 disabled . 1 enabled . sd gamma correction enable 0 disabled . 1 enab l ed. s d gamma correction curve select 0 gamma c orrection curve a . 1 gamma c orrection curve b . 0x89 sd mode register 8 sd undershoot limiter 0 0 disabled . 0x00 0 1 ?11 ire . 1 0 ?6 ire . 1 1 ?1.5 ire . reserved 0 0 must be written to this bit . sd b lack b urst o utput on dac l uma 0 disabled . 1 enabled . sd c hroma d elay 0 0 disabled . 0 1 four clock cycles . 1 0 eight clock cycles . 1 1 reserved . reserved 0 0 0 must be written to these bits . 1 w hen set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. when set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. table 30 . register 0x8a to register 0x98 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x8a sd timing register 0 sd slave/master mode 0 slave mode . 0x08 1 master mode . sd timing mode 0 0 mode 0 . 0 1 mode 1 . 1 0 mode 2 . 1 1 mode 3 . reserved 1 sd luma delay 0 0 no delay . 0 1 two clock cycles . 1 0 four clock cycles . 1 1 six clock cycles . sd minimum luma value 0 ?40 ire . 1 ?7.5 ire . sd t iming reset 0 normal operation 1 freezes the counters; t his bit must be set back to zero to reset the counters and resume operation .
data sheet ADV7344 rev. b | page 43 of 108 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x8b sd timing register 1 (a pplicable in master modes only, that is, subaddress 0x8a, b it 0 = 1) sd hsync w idth 0 0 t a = one clock cycle . 0x00 0 1 t a = four clock cycles . 1 0 t a = 16 clock cycles . 1 1 t a = 128 clock cycles . sd hsync to vsync d elay 0 0 t b = 0 clock cycles . 0 1 t b = four clock cycles . 1 0 t b = eight clock cycle .s 1 1 t b = 18 clock cycles . sd hsync to vsync rising e d ge delay (mode 1 o nly) x 2 0 t c = t b. x 2 1 t c = t b + 32 s . sd vsync width (mode 2 only) 0 0 one clock cycle . 0 1 four clock cycles . 1 0 16 clo ck cycles . 1 1 128 clock cycles . sd hsync to p ixel data a djust 0 0 0 clock cycles . 0 1 one clock cycle . 1 0 two clock cycles . 1 1 three clock cycles . 0x8c sd f sc regis ter 0 3 subcarrier frequency bits[7:0] x x x x x x x x subcarrier f requency bits[7:0] . 0x1f 0x8d sd f sc register 1 3 subcarrier frequency bits[15:8] x x x x x x x x subcarrier f requency bits[15:8] . 0x7c 0x8e sd f sc register 2 3 subcarrier frequency bits[23:16] x x x x x x x x subcarrier f requency bits[23:16] . 0xf0 0x8f sd f sc register 3 3 subcarrier frequency bits[31:24] x x x x x x x x subcarrier f requency bit s[31:24] . 0x21 0x90 sd f sc p hase subcarrier phase bits[9:2] x x x x x x x x subcarrier p hase bits[9:2] . 0x00 0x91 sd c losed c aptioning extended data on even fie lds x x x x x x x x extended d ata bits[7:0] . 0x00 0x92 sd c losed c aptioning extended data on even fields x x x x x x x x extended d ata bits[15:8] . 0x00 0x93 sd closed c aptioning data on odd fields x x x x x x x x data bits[7:0] . 0x00 0x94 sd closed c aptioning data on odd fields x x x x x x x x data bits[15:8] . 0x00 0x95 sd pedestal register 0 pedestal on odd fields 17 16 15 14 13 12 11 10 setting any of these bits to 1 disables pedestal on the line number indicated by the bit settings . 0x00 0x96 sd pedestal register 1 pedestal on o dd fi elds 25 24 23 22 21 20 19 18 0x00 0x97 sd pedestal register 2 pedestal on even fields 17 16 15 14 13 12 11 10 0x00 0x98 sd pedestal register 3 pedestal on even fields 25 24 23 22 21 20 19 18 0x00 1 x = logic 0 or logic 1. 2 x = dont care. 3 sd subcarrier frequency registers default to ntsc subcarrier frequency values.
ADV7344 data sheet rev. b | page 44 of 108 table 31 . register 0x99 to register 0xa5 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x99 sd cgms/wss 0 sd cgms data x x x x cgms data bits[c19:c16] 0x00 sd cgms crc 0 disabled 1 enabled sd cgms on odd fields 0 disabled 1 enabl ed sd cgms on even fields 0 disabled 1 enabled sd wss 0 disabled 1 enabled 0x9a sd cgms/wss 1 sd cgms/ wss data x x x x x x cgms data bits[c1 3:c8] or wss d ata bi ts[w13:w8] 0x00 sd cgms data x x cgms data bits[c15:c14] 0x9b sd cgms/wss 2 sd cgms/wss data x x x x x x x x cgms d ata bits[ c7:c0] o r wss d ata bits[w7:w0] 0x00 0x9c sd scale lsb lsbs for sd y scale value x x sd y s cale bits[1:0] 0x00 lsbs for sd cb scale value x x sd cb scale bits[1:0] lsbs for sd cr scale value x x sd cr s cale bits[1:0] lsbs for sd f sc p has e x x subcarrier p hase bits[1:0] 0x9d sd y s cale sd y scale value x x x x x x x x sd y s cale bits[ 9 :2] 0x00 0x9e sd cb scale sd cb scale value x x x x x x x x sd cb s cale bits[9:2] 0x00 0x9f sd cr s cale sd cr scale value x x x x x x x x sd cr s cale bits[9:2] 0x00 0xa0 sd h ue a djust sd hue adjust value x x x x x x x x sd hue a djust bits[7:0] 0x00 0xa1 sd brightness/wss sd brightness value x x x x x x x sd b rightness bits[6:0] 0x00 sd blank wss data 0 disabled 1 enabled 0xa2 sd l uma ssaf sd luma ssaf gain/a ttenua tion (o nly applica ble if register 0x87, bit 4 = 1) 0 0 0 0 ?4 db 0x00 0 1 1 0 0 db 1 1 0 0 +4 db reserved 0 0 0 0 0xa3 sd dnr 0 coring g ain b order (i n dnr mode , the values in brackets apply ) 0 0 0 0 no gain 0x00 0 0 0 1 +1/16 [?1/8] 0 0 1 0 +2/16 [?2/8] 0 0 1 1 +3/16 [?3/8] 0 1 0 0 +4/16 [?4/8] 0 1 0 1 +5/16 [?5/8] 0 1 1 0 +6/16 [?6/8] 0 1 1 1 +7/16 [?7/8] 1 0 0 0 +8/16 [?1] coring g ain data (i n dnr mod e, the values in brackets apply ) 0 0 0 0 no gain. 0 0 0 1 +1/16 [?1/8] 0 0 1 0 +2/16 [?2/8] 0 0 1 1 +3/16 [?3/8] 0 1 0 0 +4/16 [?4/8] 0 1 0 1 +5/ 16 [?5/8] 0 1 1 0 +6/16 [?6/8] 0 1 1 1 +7/16 [?7/8] 1 0 0 0 +8/16 [?1]
data sheet ADV7344 rev. b | page 45 of 108 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0xa4 sd dnr 1 dnr t hreshold 0 0 0 0 0 0 0 0x00 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63 bo rder a rea 0 two pixels 1 four pixels block s ize control 0 eight pixels 1 16 pixels 0xa5 sd dnr 2 dnr i nput s elect 0 0 1 filter a 0x00 0 1 0 filter b 0 1 1 filter c 1 0 0 filter d dnr m ode 0 dnr mode 1 dnr sharpness mode dnr b lock o ffset 0 0 0 0 0 pixel offset 0 0 0 1 one - pixel offset 1 1 1 0 14- pixel offset 1 1 1 1 15- pixel offset 1 x = logic 0 or logic 1. table 32 . register 0xa6 to register 0xbb sr7 to bit number 1 register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0xa6 sd gamma a0 sd gamma curve a (point 24) x x x x x x x x a0 0x00 0xa7 sd gamma a1 sd gamma curve a (point 32) x x x x x x x x a1 0x00 0xa8 sd gamma a2 sd gamma curve a (point 48) x x x x x x x x a2 0x00 0xa9 sd gamma a3 sd gamma curve a (point 64) x x x x x x x x a3 0x00 0xaa sd gamma a4 sd gamma curve a (point 80) x x x x x x x x a4 0x00 0xab sd gamma a5 sd gamma curve a (point 96) x x x x x x x x a5 0x00 0xac sd gamma a6 sd gamma curve a (point 128) x x x x x x x x a6 0x00 0xad sd gamma a7 sd gamma curve a (point 160) x x x x x x x x a7 0x00 0xae sd gamma a8 sd gamma curve a (point 192) x x x x x x x x a8 0x00 0xaf sd gamma a9 sd gamma curve a (point 224) x x x x x x x x a9 0x00 0xb0 sd gamma b0 sd gamma curve b (point 24) x x x x x x x x b0 0x00 0xb1 sd gamma b1 sd gamma curve b (point 32) x x x x x x x x b1 0x00 0xb2 sd gamma b2 sd gamma curve b (point 48) x x x x x x x x b2 0x00 0xb3 sd gamma b3 sd gamma curve b (poin t 64) x x x x x x x x b3 0x00 0xb4 sd gamma b4 sd gamma curve b (point 80) x x x x x x x x b4 0x00 0xb5 sd gamma b5 sd gamma curve b (point 96) x x x x x x x x b5 0x00 0xb6 sd gamma b6 sd gamma curve b (point 128) x x x x x x x x b6 0x00 0xb7 sd gamma b7 sd gamma curve b (point 160) x x x x x x x x b7 0x00 0xb8 sd gamma b8 sd gamma curve b (point 192) x x x x x x x x b8 0x00 0xb9 sd gamma b9 sd gamma curve b (point 224) x x x x x x x x b9 0x00 0 xba sd brightness d etect sd brightness value x x x x x x x x read only 0xxx
ADV7344 data sheet rev. b | page 46 of 108 sr7 to bit number 1 register reset sr0 register bit description 7 6 5 4 3 2 1 0 setting value 0xbb field count field count x x x read only 0x0x reserved 0 0 0 reserved encoder v ersion c ode 0 0 read only; first encoder ver sion 2 0 1 read only; s econd encoder ver sion 1 x = logic 0 or logic 1. 2 see the hd interlace externa l p_hsync and p_vsync considerations section for information about the first encoder revision. table 33 . register 0xbd to register 0xc8 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0xbd sd csc matrix 1 sd csc matrix c oe ffici ent x x x x x x x x bits [7:0] for a1 0x42 0xbe sd csc matrix 2 sd csc matrix c oefficient x x x x x x x x bits [7:0] for a2 0x81 0xbf sd csc matrix 3 sd csc m atrix c oefficient x x x x x x x x bits [7:0] for a3 0x19 0xc0 sd c sc matrix 4 sd csc matrix c oefficient x x x x x x x x bits [7:0] for a4 0x10 0xc1 sd csc matrix 5 sd csc matrix c oefficient x x x x x x x x bits [7:0] for b1 0x70 0xc2 sd csc matrix 6 sd csc matrix c oefficient x x x x x x x x bits [7:0] for b2 0x5e 0xc3 sd csc matrix 7 sd csc matrix c oefficient x x x x x x x x bits [7:0] for b3 0x12 0xc4 sd csc matrix 8 sd csc matrix c oefficient x x x x x x x x bits [7:0] for b4 0x80 0xc5 sd csc matrix 9 sd csc matrix c oefficien t x x x x x x x x bits [7:0] for c1 0x26 0xc6 sd csc matrix 10 sd csc matrix c oefficient x x x x x x x x bits [7:0] for c2 0x4a 0xc7 sd csc matrix 11 sd csc matrix c oefficient x x x x x x x x bits [7:0] for c3 0x70 0xc8 sd csc ma trix 12 sd csc matrix c oefficient x x x x x x x x bits [7:0] for c4 0x80 1 x = logic 0 or logic 1.
data sheet ADV7344 rev. b | page 47 of 108 table 34 . register 0xc9 to register 0x ce sr7 to bit number reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0x c9 teletext c ontrol teletext e nable 0 disabled . 0x00 1 enabled . teletext request m ode 0 line request signal . 1 bit request signal . teletext i nput pin s elect 0 0 s_ vsync . 0 1 p_ vsync . 1 0 c0 . 1 1 reserved . reserved 0 0 0 0 reserved . 0x ca teletext request control teletext request falling edge p osition control 0 0 0 0 0 clock cycles . 0x00 0 0 0 1 one clock cycle . 1 1 1 0 14 clock cycles . 1 1 1 1 15 clock cycles . teletext request rising edge position c ontrol 0 0 0 0 0 clock cycles . 0 0 0 1 one clock cycle . 1 1 1 0 14 clock cycles . 1 1 1 1 15 clock cycles . 0x cb ttx line enable 0 teletext on o dd f ields 22 21 20 19 18 17 16 15 setting any of these bits to 1 enables t eletext on the line numbe r indicated by the bit settings . 0x00 0x cc ttx line enable 1 teletext on odd f ield s 14 13 12 11 10 9 8 7 0x00 0x cd ttx line enable 2 teletext on even f ields 22 21 20 19 18 17 16 15 0x00 0x ce ttx line enable 3 teletext on even f ields 14 13 12 11 10 9 8 7 0x00 table 35 . register 0xe0 to register 0xf1 sr7 to bit number 1 reset sr0 register bit description 7 6 5 4 3 2 1 0 register setting value 0xe0 macrovision mv control bits x x x x x x x x 0x00 0xe1 macrovision mv control b its x x x x x x x x 0x00 0xe2 macrovision mv con trol b its x x x x x x x x 0x00 0xe3 macrovision mv control b its x x x x x x x x 0x00 0xe4 macrovision mv control b its x x x x x x x x 0x00 0xe5 macrovision mv control b its x x x x x x x x 0x00 0xe6 macrovision mv control b its x x x x x x x x 0x00 0xe7 macrovision mv control b its x x x x x x x x 0x00 0xe8 macrovision mv control b its x x x x x x x x 0x00 0xe9 macrovision mv control b its x x x x x x x x 0x00 0xea macrovision mv control b its x x x x x x x x 0x00 0xeb macrovision mv control b its x x x x x x x x 0x00 0xec macrovision mv control b its x x x x x x x x 0x00 0xed macrovision mv control b its x x x x x x x x 0x00 0xee macrovi sion mv control b its x x x x x x x x 0x00 0xef macrovision mv control b its x x x x x x x x 0x00 0xf0 macrovision mv control b its x x x x x x x x 0x00 0xf1 macrovision mv c ontrol bits 0 0 0 0 0 0 0 x bits[7:1] must be 0 . 0 x00 1 x = logic 0 or logic 1.
ADV7344 data sheet rev. b | page 48 of 108 input configuration the ADV7344 supports a number of different input modes. the desired input mode is selected using subaddress 0x01, bits[6:4]. the ADV7344 defaults to standard definition only (sd only) on power-up. table 36 provides an overview of all possible input configurations. each input mode is described in detail in the following sections. standard definition only subaddress 0x01, bits[6:4] = 000 standard definition (sd) ycrcb data can be input in 4:2:2 format. standard definition (sd) rgb data can be input in 4:4:4 format. a 27 mhz clock signal must be provided on the clkin_a pin. input synchronization signals are provided on the s_hsync and s_vsync pins. 8-/10-bit 4:2:2 ycrcb mode subaddress 0x87, bit 7 = 0; subaddress 0x88, bit 3 = 0 in 8-/10-bit 4:2:2 ycrcb input mode, the interleaved pixel data is input on pin s9 to pin s2/s0 (o r pin y9 to pin y2/y0, depending on subaddress 0x01, bit 7), with pin s0/y0 being the lsb in 10-bit input mode. the itu-r bt.601/656 input standard is supported. embedded eav/sav timing codes are also supported. 16-/20-bit 4:2:2 ycrcb mode subaddress 0x87, bit 7 = 0; subaddress 0x88, bit 3 = 1 in 16-/20-bit 4:2:2 ycrcb input mode, the y pixel data is input on pin s9 to pin s2/s0 (or pin y9 to pin y2/y0, depending on subaddress 0x01, bit 7), with pin s0/y0 being the lsb in 20-bit input mode. the crcb pixel data is input on pin y9 to pin y2/y0 (or pin c9 to pin c2/c0, depending on subaddress 0x01, bit 7), with pin y0/c0 being the lsb in 20-bit input mode. embedded eav/sav timing codes are not supported; therefore, so an external synchronization is needed in this mode. 24-/30-bit 4:4:4 rgb mode subaddress 0x87, bit 7 = 1 in 24-/30-bit 4:4:4 rgb input mode, the red pixel data is input on pin s9 to pin s2/s0, the green pixel data is input on pin y9 to pin y2/y0, and the blue pixel data is input on pin c9 to pin c2/c0. the s0, y0, and c0 pins are the respective bus lsbs in 30-bit input mode. embedded eav/sav timing codes are not supported with sd rgb input mode. also, master timing mode is not supported for sd rgb input mode, therefore, external synchronization must be used. mpeg2 decoder clkin_a s[9:0] or y[9:0] 1 27mhz ycrcb ADV7344 notes 1 selected by subaddress 0x01, bit 7. s_vsync, s_hsync 2 10 0 6400-051 figure 50. sd only example application
data sheet ADV7344 rev. b | page 49 of 108 table 36 . input configuration s y c input mode 1 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 000 sd o nly y/c/s b us s wap (0x01[7]) = 0 8- /10 -b it ycrcb 2 , 3 ycrcb 16- /20 -b it ycrcb 2 , 3 , 4 y crcb y/c/s bus s wap (0x01[7]) = 1 8- /10 -b it ycrcb 2 , 3 ycrcb 16- /20 -b it ycrcb 2 , 3 , 4 y crcb sd rgb i nput e nable (0x87[7]) = 1 24- /30 -b it rgb 4 r g b 001 ed/hd - sdr o nly 3 , 5 , 6 , 7 ed/hd rgb i nput e nable (0x35[1]) = 0 16- /20 -b it ycrcb y crcb 24- /30 -b it ycrcb cr y cb ed/hd rgb i nput e nable (0x35[1]) = 1 24- /30 -b it rgb 4 r g b 010 ed/hd - ddr only (8 - /1 0-b it) 3 , 6 , 7 ycrcb 011 sd, ed/hd - sdr (24 - /30 - b it) 3 , 6 , 7 , 8 ycrcb (sd) y (ed/hd) crcb (ed/hd) 100 sd, ed/hd - ddr (16 - /20 - b it) 3 , 6 , 7 , 8 ycrcb (sd) ycrcb (ed/hd) 111 ed only (54 mhz) (8 - /10 - b it) 3 , 6 , 7 ycrcb 1 the input mode is determined by subaddress 0x01, bits[6:4]. 2 in sd onl y (ycrcb) mode, the format of the input data is determined by subaddress 0x88, bits[4:3]. see table 29 for more information. 3 for 8 - /16 - /24 - bit inputs, only the eight most significant bits (msbs) of each applicable input bus ar e used. 4 external synchronization signals must be used in this input mode. embedded eav/sav timing codes are not supported. 5 in ed/hd - sdr only (ycrcb) mode, the format of the input data is determined by subaddress 0x33, bit 6. see table 22 for more information. 6 ed = enhanced definition = 525p and 625p. 7 the bus width of the ed/hd input data is determined by subaddress 0x33, bit 2 (0 = 8 - bit input , 1 = 10 - bit input ). see table 22 for more informati on. 8 the bus width of the sd input data is determi ned by subaddress 0x88, bits[ 4 :] (0 0 = 8 - bit, 11 = 16 - bit , 10 = 10 - bit , 1 1 = 2 0- bit). see table 29 for more information.
ADV7344 data sheet rev. b | page 50 of 108 enhanced definition/ high definition only subaddress 0 x 01, bits[6:4] = 001 or 010 enhanced definition (ed) or high definition (hd) ycrcb data can be input in either 4:2:2 or 4:4:4 format . if desired, dual data rate (ddr) pixel data inputs can be employed (4:2:2 format only). enhanced definition (ed) or high definition (hd) rgb data can be input in 4:4:4 format (single data rate only). the clock signal must be provided on the clkin_a pin. input synchronization signals are provided on the p_hsync , p_vsync , and p_blank pins. 16- /20 - bit 4:2:2 ycrcb mode (sdr) subaddress 0x35, bit 1 = 0; subaddress 0x33, bit 6 = 1 in 16 - /20 - bit 4:2:2 ycrcb input mode, the y pixel data is input on pin y9 to pin y2/y0, with pin y0 being the lsb in 20 - bit input mode. the crcb pixel data is input on pin c9 to pin c2/c0, with pin c0 being the lsb in 20 - bit input mode. 8- /10 - bit 4:2:2 ycrcb mode (ddr) subaddress 0x35, bit 1 = 0; subaddress 0x33, bit 6 = 1 in 8 - /10 - bit ddr 4:2:2 ycrcb input mode, the y pixel data is input on pin y9 to pin y2/y0 on either the rising or falling edge of clkin_a. pin y0 is the lsb in 10 - bit input mode. the crcb pixel data is also input on pin y9 to pin y2/y0 on the opposite edg e of clkin_a. pin y0 is the lsb in 10 - bit input mode. whe ther the y data is clocked in on the rising or falling edge of clkin_a is determined by subaddress 0x01, bits[2:1] (see figure 51 and figure 52). 3ff 00 00 x y y0 y1 cr0 clkin_a notes 1. subaddress 0x01 [2:1] should be set to 00 in this case. y[9:0] cb0 06400-052 figure 51 . ed/hd - ddr input sequence (eav/sav) option a 3ff 00 00 xy cb0 cr0 y1 clkin_ a y[9:0] y0 notes 1. subaddress 0x01 [2:1] should be set to 11 in this case. 06400-053 figure 52 . ed/hd - ddr input sequence (eav/sav) option b 24- /30 - bit 4:4:4 ycrcb mode subaddress 0x35, bit 1 = 0; subaddress 0x33, bit 6 = 0 in 24- /30 - bit 4:4:4 ycrcb input mode, the y pixel data is input on pin y9 to pin y2/y0, with pin y0 being the lsb in 30 - bit input mode. the cr pixel data is input on pin s9 to pin s2/s0, with pin s0 being the lsb in 30 - bit input mode. the cb pixel data is in put on pin c9 to pin c2/c0, with pin c0 being the lsb in 30 - bit input mode. 24- /30 - bit 4:4:4 rgb mode subaddress 0x35, bit 1 = 1 in 24 - /30 - bit 4:4:4 rgb input mode, the red pixel data is input on pin s9 to pin s2/s0, the green pixel data is input on pin y9 to pin y2/y0, and the blue pixel data is input on pin c9 to pin c2/c0. the s0, y0, and c0 pins are the respective bus lsbs in 30 - bit input mode. mpeg2 decoder clkin_ a c[9:0] s[9:0] y[9:0] interlaced to progressive ycrcb ADV7344 p_vsync, p_hsync, p_blank 10 cb 10 cr 10 y 3 06400-054 figure 53 . ed/hd only example application simultaneous standar d definition and enha nced definition/high definition subaddress 0 x 01, bits[6:4] = 011 or 100 the ADV7344 is able to simultaneously process sd 4:2:2 ycrcb data and ed/hd 4:2:2 ycrcb data. the 27 mhz sd clock signal must be provided on the clkin_a pin. the ed/hd clock signal mus t be provided on the clkin_b pin. sd input synchronization signals are provided on the s_hsync and s_vsync pins. ed/hd input synchronization signals are provided on the p_hsync , p_vsync , and p_blank pins. sd 8 - /10 - bit 4:2:2 ycrcb and ed/hd - sdr 16 - /20 - bit 4:2:2 ycrcb the sd 8 - /10 - bit 4:2:2 ycrcb pixel data is input on pin s9 to pin s2/s0, with pin s0 being the lsb in 10 - bit input mode. the ed/hd 16 - /20 - bit 4:2:2 y pixel data is input on pin y9 to pin y2/y0, with pin y0 being the lsb in 20 - bit input mode. the ed/hd 16 - /20 - bit 4:2:2 crcb pixel data is input on pin c9 to pin c2/c0, with pin c0 being the lsb in 20 - bit input mode. sd 8 - /10 - bit 4:2:2 ycrcb and ed/hd - ddr 8 - /10 - bit 4:2:2 ycrcb the sd 8 - /10 - bit 4:2:2 ycrcb pixel data is input on pin s9 to pin s2/s0, with pin s0 being the lsb in 10 - bit input mode . the ed/hd - ddr 8 - /10 - bit 4:2:2 y pixel data is input on pin y9 to pin y2/y0 upon the rising or falling edge of clkin_b. pin y0 is the lsb in 10 - bit input mode. the ed/hd - ddr 8 - /10 - bit 4:2:2 crcb pixel data is also input on pin y9 to pin y2/y0 on the opposite edge of clkin_b. pin y0 is the lsb in 10 - bit input mode.
data sheet ADV7344 rev. b | page 51 of 108 whether t he ed/hd y data is c locked in on the rising or falling edge of clkin_b is determined by subaddress 0x01, b its[2:1] (s ee the input sequence shown in figure 51 and figure 52). clkin _a clki n_ b s[9:0] c[9:0] y[9:0] ADV7344 ed decoder s_vsyn c, s_hsync p_vsy nc , p_hsy nc , p_bl an k 27m hz 10 crcb 10 y 3 2 ycrcb 27mhz 10 sd decoder 525p or 625p 06400-055 figure 54 . simul taneous sd and ed example application clkin _a clki n_ b s[9:0] c[9:0] y[9:0] ADV7344 hd decoder s_vsyn c, s_hsync p_vsy nc , p_hsy nc , p_bl an k 74.25m hz 10 crcb 10 y 3 2 ycrcb 27mhz 10 sd decoder 1080i or 720p or 1035i 06400-056 figure 55 . simultaneous sd and hd example application enhanced definition only (at 54 mh z) subaddress 0x0 1 , bits[6:4] = 111 enhanced definition (ed) ycrcb data can be input in an interleaved 4:2:2 format on an 8 - /10 - bit bus at a rate of 54 mhz. a 54 mhz clock signal must be provided on the clkin_a pin. input synchronization signals are provided on the p_hsync , p_vsync , and p_bl ank pins. the interleaved pixel data is input on pin y9 to pin y2/y0, with pin y0 being the lsb in 10 - bit input mode. 3ff 00 00 xy cb0 y0 y1 cr0 clkin_a y[9:0] 06400-057 figure 56 . ed only (at 54 mhz) input sequence (eav/sav) mpeg2 deco der clkin_a y[9:0] 54mhz ADV7344 p_vsync, p_hsync, p_blank ycrcb 10 ycrcb 3 interlaced to progressive 06400-058 figure 57 . ed only (at 54 mhz) example application
ADV7344 data sheet rev. b | page 52 of 108 output configuration the ADV7344 supports a number of different output configurations. tabl e 37 to tabl e 40 list all possible output configurations. table 37 . sd only output configurations rgb/yprpb output select 1 ( subaddress 0x02, bit 5) sd dac output 2 ( subaddress 0x82, bit 2) sd dac output 1 ( subaddress 0x82, bit 1) sd luma/chroma swap ( subddress 0x84, bit 7) dac 1 dac 2 dac 3 dac 4 dac 5 da c 6 0 0 0 0 g b r cvbs luma chroma 0 0 0 1 g b r cvbs chroma luma 0 0 1 0 cvbs luma chroma g b r 0 0 1 1 cvbs chroma luma g b r 0 1 0 0 cvbs b r g luma chroma 0 1 0 1 cvbs b r g chroma luma 0 1 1 0 g luma chroma cvbs b r 0 1 1 1 g chroma luma cvbs b r 1 0 0 0 y pb pr cvbs luma chroma 1 0 0 1 y pb pr cvbs chroma luma 1 0 1 0 cvbs luma chroma y pb pr 1 0 1 1 cvbs chroma luma y pb pr 1 1 0 0 cvbs pb pr y luma chroma 1 1 0 1 cvbs pb pr y chroma luma 1 1 1 0 y luma chroma cvbs pb pr 1 1 1 1 y chroma luma cvbs pb pr 1 if sd rgb output is selected, a color reversal is poss ible using subaddress 0x86, bit 7. table 38 . ed/hd only output configurations rgb/yprpb output select ( subaddress 0x02, bit 5) ed/hd color dac swap ( subaddress 0x35, bit 3) dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 0 0 g b r n/a n/a n/a 0 1 g r b n/ a n/a n/a 1 0 y pb pr n/a n/a n/a 1 1 y pr pb n/a n/a n/a table 39 . simultaneous sd and ed/hd output configurations rgb/yprpb output select ( subaddress 0x02, bit 5) ed/hd color dac swap ( subaddress 0x35, bit 3) sd luma/chroma swa p ( subaddress 0x84, bit 7) dac 1 (ed/hd) dac 2 (ed/hd) dac 3 (ed/hd) dac 4 (sd) dac 5 (sd) dac 6 (sd) 0 0 0 g b r cvbs luma chroma 0 0 1 g b r cvbs chroma luma 0 1 0 g r b cvbs luma chroma 0 1 1 g r b cvbs chroma luma 1 0 0 y pb pr cvbs luma chroma 1 0 1 y pb pr cvbs chroma luma 1 1 0 y pr pb cvbs luma chroma 1 1 1 y pr pb cvbs chroma luma table 40 . ed only (at 54 mhz) output configurations rgb/yprpb output select ( subaddress 0x02, bit 5) ed/hd color dac swap ( subaddress 0x3 5, bit 3) dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 0 0 g b r n/a n/a n/a 0 1 g r b n/a n/a n/a 1 0 y pb pr n/a n/a n/a 1 1 y pr pb n/a n/a n/a
data sheet ADV7344 rev. b | page 53 of 108 design features output oversampling the ADV7344 includes two on - chip phase - locked loops (plls) that allow for ove rsampling of sd, ed, and hd video data. table 41 shows the various oversampling rates supported in the ADV7344. sd only, ed only, and hd only modes pll 1 is used in sd only, ed only, and hd only modes. pll 2 is unused in these modes. pll 1 is disabled by default and can be enabled using subaddress 0x00, bit 1 = 0. sd and ed/hd simultaneous modes both pll 1 and pll 2 are used in simultaneous modes. the use of two plls allows for independent oversampling of sd and ed/hd video. pll 1 is used to oversample sd video data, and pll 2 is used to oversample ed/hd video data. in simultaneous modes, pll 2 is always enabled. pll 1 is disabled by default and can be enabled using subaddress 0x00, bit 1 = 0. external sync pola rity for sd and ed/hd modes, the ADV7344 parts typically expect hs and vs to be low during their respective blanking periods. h owever , w hen the cea861 compliance bit (0x39, bit 5 for ed/hd modes and 0x86, bit 3 for sd modes) is enabled, the part expects th e hs or vs to be active low or high depending on the input format selected (0x30 bits [7:3]). if a different polarity other than the default is needed for ed/hd modes, 0x3a bits [2:0] can be used to invert phsyncb, pvsyncb or pblankb individually regardle ss of whether cea- 861- b mode is enabled. it is not possible to invert s_hsync or s_vsync. table 41 . output oversampling modes and rates input mode subaddress 0x01 bits [6:4] pll and oversampling control subaddress 0x00, bit 1 overs ampling mode and rate 000 sd only 1 sd (2) 000 sd only 0 sd (16) 001/010 ed only 1 ed (1) 001/010 ed only 0 ed (8) 001/010 hd only 1 hd (1) 001/010 hd only 0 hd (4) 011/100 sd and ed 1 sd (2) and ed ( 8) 011/100 sd and ed 0 sd (16) and ed ( 8) 011/100 sd and hd 1 sd (2) and hd (4) 011/100 sd and hd 0 sd (16) and hd ( 4) 111 ed only (at 54 mhz) 1 ed only (at 54 mhz) (1) 111 ed only (at 54 mhz) 0 ed only (at 54 mhz) (8)
ADV7344 data sheet rev. b | page 54 of 108 hd interlace externa l p_h sync and p_v sync considerations if the encoder r ev ision code (subaddress 0xb b, bits[7:6]) = 01 or higher , the user should set subaddress 0x02, bit 1 to high to ensure exactly correct timing in the hd interlace modes when using the p_h sync and p_v sync synchronization signals. if this bit is set to low, the first active pixel on each line is masked and pr and pb outputs are swapped when using the ycrcb 4:2:2 input format. setting subaddress 0x02, bit 1 low causes the encod er to behave in the same way as the first version of silicon (that is, this setting is backward compatible). if the encoder revision code (subaddress 0xbb, bits[7:6]) = 00, the setting of subaddress 0x02, bit has no effect. in this version of the encoder, the first active pixel is masked and pr and pb outputs are swapped when using the ycrcb 4:2:2 format in hd interlace modes with the p_h sync and p_v sync synchron - ization signals. to avoid these limitations, use the newer revision of silicon or a different type of synchronization. these considerations apply only to the hd interlace mode s with external p_h sync and p_v sync s ynchronization (eav/sav mode is not affected and always has exactly correct timing ). there is no negative effect in setting subaddress 0x02, bit 0 to high, and this bit can remain high for all the other video standards. ed/hd timing reset subaddress 0x34, bit 0 an ed/hd timing reset is achieved by toggling the ed/hd timi ng reset control bit (subaddress 0x34, bit 0) from 0 to 1. in this state, the horizontal and vertical counters remain reset. when this bit is set back to 0, the internal counters resume counting. this timing reset applies to the ed/hd timing counters only. sd subcarrier freque ncy lock subcarrier frequency lock (sfl) mode in this mode (subaddress 0x84, bits[2:1] = 11), the ADV7344 can be used to lock to an external video source. the sfl mode allows the ADV7344 to automatically alter the subcarrier frequency to compensate for line length variations. when the part is connected to a device such as an adv7403 video decoder (see figure 58) that outputs a digital data stream in the sfl fo rmat, the part automatically changes to the compensated subcarrier frequency on a line - by - line basis. this digital data stream is 67 bits wide, and the subcarrier is contained in bit 0 to bit 21. each bit is two clock cycles long. sd vcr ff/rw sync subadd ress 0x82, bit 5 in dvd record applications where the encoder is used with a decoder, the vcr ff/rw sync control bit can be used for nonstandard input video, that is, in fast forward or rewind mode . in fast forward mode, the sync information at the start o f a new field in the incoming video usually occurs before the correct number of lines/fields is reached. in rewind mode, this sync signal usually occurs after the total number of lines/fields is reached. conventionally, this means that the output video has corrupted field signals because one signal is generated by the incoming video and another is generated when the internal line/field counters reach the end of a field. when the vcr ff/rw sync control is enabled (subaddress 0x82, bit 5), the line/field counters are updated according to the incoming vsync signal and when the analog output matches the incoming vsync signal. this control is available in all slave - timing modes except slave mode 0. llc1 sfl p19 to p10 adv7403 video decoder clkin_a sfl y9 to y0/ s9 to s0 5 rtc low 128 time slot 01 13 0 14 21 19 f sc pll increment 2 valid sample invalid sample 6768 0 reset bit 4 reserved ADV7344 8/line locked clock 5 bits reserved 1 for example, vcr or cable. 2 f sc pll increment is 22 bits long. value loaded into ADV7344 f sc dds register is f sc pll increments bits[21:0] plus bits[0:9] of subcarrier frequency registers. 3 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 4 reset ADV7344 dds. 5 selected by subaddress 0x01, bit 7. composite video 1 h/l transition count start 14 bits subcarrier phase sequence bit 3 dac 1 dac 2 dac 3 dac 4 dac 5 dac 6 4 bits reserved 06400-063 figure 58 . sd subcarrier frequency lock timing and connections diagram (subaddress 0x84, bits [2:1] = 11)
data sheet ADV7344 rev. b | page 55 of 108 vertical blanking in terval subaddress 0x31, bit 4; subaddress 0x83, bit 4 the ADV7344 is able to accept input data that contains vbi data (such as cgms, wss, vits) in sd, ed, and hd modes.if vbi is disabled (subaddress 0x31, bit 4 for ed/hd; subaddress 0x83, bit 4 for sd), vbi data is not present at the output and the entire vbi is blanked. these control bits are valid in all master and slave timing modes. for the smpte 293m (525p) standard, vbi data can be inserted on l ine 13 to line 42 of each frame or on line 6 to line 43 for the itu - r bt.1358 (625p) standard. vbi data can be present on line 10 to line 20 for ntsc and on line 7 to line 22 for pal. in sd timing mode 0 (slave option), if vbi is enabled, the blanking bit in the eav/sav code is overwritten. it is possible to use vbi in this timing mode as well. if cgms is enabled and vbi is disabled, the cgms data is , nevertheless , available at the output . sd subcarrier freque ncy control subaddress 0x8c to subaddress 0x8f the ADV7344 is able to generate the color subcarrier used in cvbs and s - video (y - c) outputs from the input pixel clock. four 8 - bit registers are used to set up the subcarrier frequency. the value of thes e registers is calculated using 32 2 mhz 27 = line videooneincyclesclk of number line videoonein periods subcarrier of number register frequency subcarrier where the sum is rounded to the nearest integer. for example, in ntsc mode 569408543 2 1716 5.227 32 = ? ? ? ? ? ? = value register subcarrier where: subcarrier register value = 569408543d = 021f07c1f sd f sc regist er 0: 0x1f sd f sc register 1: 0x7c sd f sc register 2: 0xf0 sd f sc register 3: 0x21 programming the f sc the subcarrier frequency register value is divided into four f sc registers , as shown in the previous example. the four subcarrier frequency registers must be update d sequentially, starting with s ubcarrier f reque ncy register 0 and end ing with subcarrier f requency r egister 3. the subcarrier frequency updates only after the last subcarrier frequency register byte has been received by the ADV7344. the sd input standard autod etection feature must be disabled. typical f sc values table 42 outlines the values that should be written to the subcarrier frequency registers for ntsc and pal b/d/g/h/i. table 42 . typi cal f sc values subaddress description ntsc pal b/d/g/h/i 0x8c f sc 0 0x1f 0xcb 0x8d f sc 1 0x7c 0x8a 0x8e f sc 2 0xf0 0x09 0x8f f sc 3 0x21 0x2a sd noninterlaced mod e subaddress 0x8 8 , bit 1 the ADV7344 supports a n sd noninterlaced mode. using this mode, progr essive inputs at twice the frame rate of ntsc and pal (240p/59.94 hz and 288p/50 hz, respectively) can be input into the ADV7344. the sd noninterlaced mode can be enabled using subaddress 0x88, bit 1. a 27 mhz clock signal must be provided on the clkin_a p in. embedded eav/sav timing codes or external horizontal and vertical synchronization signals provided on the s_ hsync and s_v sync pins can be used to synchronize the input pixel data. all input configurations, output configurations, and features available in ntsc and pal modes are available in sd noninterlaced mode. for 240p/59.94 hz input, the ADV7344 should be configured for ntsc operation, and subaddress 0x88, bit 1 should be set to 1. for 288p/50 hz input, t he ADV7344 should be configured for pal operation , and subaddress 0x88, bit 1 should be set to 1. sd square pixel mode subaddress 0x82, bit 4 the ADV7344 supports an sd square pixel mode (subaddress 0x82, bit 4). for ntsc operation, an input clock of 24.54 54 mhz is required. the active resolution is 640 480 . f or pal operation, an input clock of 29.5 mhz is required. the active resolution is 768 576. for cvbs and s - video (y - c) outputs, the sd subcarrier frequency registers must be updated to reflect the input clock frequency used i n sd square pixel mode. the sd input standard a uto d etection feature must be disabled in sd square pixel mode. in square pixel mode , the timing diagrams shown in figure 59 and figure 60 apply.
ADV7344 data sheet rev. b | page 56 of 108 y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 272 clock 1280 clock 4 clock 4 clock 344 clock 1536 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y 06400-064 figure 59 . square pixel mode eav/sav embedded timing field pixel data pal = 308 clock cycles ntsc = 236 clock cycles cb y cr y hsync 06400-065 figure 60 . square pixel mode active pixel timing filters table 43 shows an overview of the programmable filters available on the ADV7344. table 43 . selectable filters filter subaddress sd luma lpf ntsc 0x80 sd luma lpf pal 0x80 sd luma notch ntsc 0x80 sd luma notch pal 0x80 sd luma ssaf 0x80 sd luma cif 0x80 sd luma qcif 0x80 sd chroma 0.65 mhz 0x80 sd chroma 1.0 mhz 0x80 sd chroma 1.3 mhz 0x80 sd chroma 2.0 mhz 0x80 sd chroma 3.0 mhz 0x80 sd chroma cif 0x80 sd chroma qcif 0x80 sd prpb ssaf 0x82 ed/hd chroma input 0x33 ed/hd sinc compensa tion filter 0x33 ed/hd chroma ssaf 0x33 sd internal filter response subaddress 0x80, bits[7:2]; subaddress 0x82, bit 0 the y filter supports several different frequency responses, including two low - pass responses, two notch responses, an extended (ssa f) response with or without gain boost attenuation, a cif response, and a qcif response. the prpb filter supports several different frequency responses, including six low - pass responses, a cif response, and a qcif response, as shown in figure 38 and figure 39 . if sd ssaf gain is enabled (subaddress 0x87, bit 4), there are 13 response options in the ?4 db to +4 db range . the desired response can be programmed using subaddress 0xa2. the variation in fr equency responses is shown in figure 35 to figure 37. in addition to the chroma filters listed in table 43 , the ADV7344 contains an ssaf filter that is specifically des igned for the color difference component outputs, pr and pb. this filter has a cutoff frequency of ~2.7 mhz and a gain of C 40 db at 3.8 mhz (see figure 61 ). this filter can be controlled with subaddress 0x82, bit 0.
data sheet ADV7344 rev. b | page 57 of 108 frequency (mhz) 0 gain (db) ?10 ?30 ?50 ?60 ?20 ?40 6 5 4 3 210 extended (ssaf) prpb filter mode 06400-066 figure 61 . prpb ssaf filter if this filter is disabled, one of the chroma filters shown in table 44 can be selected and used for the cvbs or luma/chroma signal. table 44 . internal filter specifications filter pass - band ripple (db) 1 3 db bandwidth (mhz) 2 luma lpf ntsc 0.16 4.24 luma lpf pal 0.1 4.81 luma notch ntsc 0.09 2.3/4.9/6.6 luma notch pal 0.1 3.1/5.6/6.4 luma ssaf 0.04 6.45 luma cif 0.127 3.02 luma qcif m onotonic 1.5 chroma 0.65 mhz monotonic 0.65 chroma 1.0 mhz monotonic 1 chroma 1.3 mhz 0.09 1.395 chroma 2.0 mhz 0.048 2.2 chroma 3.0 mhz monotonic 3.2 chroma cif monotonic 0.65 chroma qcif monotonic 0.5 1 pass - band ripple is the maximum fluctuation from the 0 db response in the pass band, measured in d ecibels . the pass band is defined to have 0 hz to fc (hz) frequen cy limits for a low - pass filter and 0 hz to f1 (hz) and f2 (hz) to infinity for a notch filter, where fc, f1, and f2 are the ?3 db points. 2 3 db bandwidth refers to the ?3 db cutoff frequency. ed/hd sinc compensation filter response subaddress 0x33, bit 3 the ADV7344 includes a filter designed to counter the effect of sinc roll - off in dac 1, dac 2, and dac 3 while operating in ed/hd mode. this filter is enabled by default. it can be disabled using subaddress 0x33, bit 3. the benefit of the filter is illustrated in figure 62 and figure 63. frequency (mhz) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 06400-067 figure 62 . ed/hd sinc compensation filter enabled frequency (mhz) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 06400-068 figure 63 . ed/hd sinc compensation filter disabled ed/hd test pattern c olor controls subaddress 0x36 to subaddress 0x38 three 8 - bit registers at subaddress 0x36 to subadd ress 0x38 are used to program the output color of the internal ed/hd test pat tern generator (subaddress 0x31, bit 2 = 1), whethe r it be the lines of the cross hatch pattern or the uniform field test pattern. they are not functional as color controls for external pixel data input. the values for the luma ( y) and the color difference (cr and cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the itu - r bt.601 - 4 standard. table 45 sh ows sample color values that can be programmed into the color registers when the output standard selection is set to eia 770.2 / eia 770. 3 (subaddress 0x30, bits[1:0] = 00).
ADV7344 data sheet rev. b | page 58 of 108 table 45 . sample color values f or eia 770.2/eia770.3 ed/hd o utput standard selection sample color y value cr value cb value white 235 (0xeb) 128 (0x80) 128 (0x80) black 16 (0x10) 128 (0x80) 128 (0x80) red 81 (0x51) 240 (0xf0) 90 (0x5a) green 145 (0x91) 34 (0x22) 54 (0x36) blue 41 (0x29) 110 (0x6e) 240 (0xf0) yellow 210 (0xd2) 146 (0x92) 16 (0x10) cyan 170 (0xaa) 16 (0x10) 166 (0xa6) magenta 106 (0x6a) 222 (0xde) 202 (0xca) color space conversi on matrix subaddress 0x03 to subaddress 0x09 the internal color space conversion (csc) matrix automatically performs all color space conversions based on the input mode programmed in the m ode s elect r egister (subaddress 0x01, bits[6:4]). table 46 and table 47 show the options available in this matrix. an sd color space conversion from rgb - in to yprpb - out is possible. an ed/hd color space conversion from rgb - in to yprpb - out is not possible. table 46 . sd color space conversion options input output 1 yprpb/rgb out ( subaddress 0x02, bit 5) rgb in/ycrcb in ( subaddress 0x87, bit 7) ycrcb yprpb 1 0 ycrcb rgb 0 0 rgb yprpb 1 1 rgb rgb 0 1 1 cvbs/yc outputs are available for all csc combinations. table 47 . ed/hd color space conversion options input output yprpb/rgb out ( subaddress 0x02, bit 5) rgb in/ycrcb in (subaddress 0x35, bit 1) ycrcb yprpb 1 0 ycrcb rgb 0 0 rgb rgb 0 1 sd manual csc matrix adjust feature the sd manual csc matrix adjust feature provides custom coefficient manipulation for rgb to ypbpr conversion (for ypbpr to rgb conversion, this matrix adjustment is not available). normally, there is no need to modify the sd matrix coefficients because the csc matrix automatically performs the color space conversion based on the output col or space selected (see table 46 ). note that bit 7 in s ubaddress 0x87 must be set to enable rgb input and, therefore, use the csc manual adjustment. the sd csc matrix scalar uses the following equations: y = (a1 r) + ( a2 g) + ( a3 b) + a4 pr = (b1 r) + ( b2 g) + ( b3 b) + b4 pb = (c1 r) + (c 2 g) + (c 3 b) + c 4 the coefficients and their default values and register locations are shown in table 48 . table 48 . sd man ual csc matrix default values coefficient subaddress default a1 0xbd 0x42 a2 0xbe 0x81 a3 0xbf 0x19 a4 0xc0 0x10 b1 0xc1 0x70 b2 0xc2 0x5e b3 0xc3 0x12 b4 0xc4 0x80 c1 0xc5 0x26 c2 0xc6 0x4a c3 0xc7 0x70 c4 0xc8 0x80 ed/hd manual csc matrix ad just feature the ed/hd manual csc matrix adjust feature provides custom coefficient manipulation for color space conversions and is used in ed and hd modes only. the ed/hd manual csc matrix adjust feature can be enabled using subaddress 0x02, bit 3. normal ly, there is no need to enable this feature because the csc matrix automatically performs the color space conversion based on the input mode chosen (ed or hd) and the input and output color spaces selected (see table 47 ). for this reason, the ed/hd manual csc matrix adjust feature is disabled by default. if rgb output is selected, the ed/hd csc matrix scalar uses the following equations: r = gy y + rv pr g = gy y ? ( gu pb ) ? ( gv pr ) b = gy y + bu pb note that subtractions are implemented in hardware. if yprpb output is selected, the following equations are used: y = gy y pr = rv pr pb = bu pb where: gy = subaddress 0x05, bits[7:0] and subaddress 0x03, bits[1:0]. gu = subaddress 0x06, bits[7:0] and subaddress 0x04, bits[7:6]. gv = subaddress 0x07, bits[7:0] and subaddress 0x04, bits[5:4]. bu = subaddress 0x08, bits[7:0] and subaddress 0x04, bits[3:2]. rv = subaddress 0x09, bits[7:0] and subaddress 0x04, bits[1:0].
data sheet ADV7344 rev. b | page 59 of 108 o n power - up, the csc matrix is programmed with the default values shown in table 49 . table 49. ed/hd manual csc matrix default values subaddress default 0x03 0x03 0x04 0xf0 0x05 0x4e 0x0 6 0x0e 0x07 0x24 0x08 0x92 0x09 0x7c when the ed/hd manual csc matrix adjust feature is enabled , the default coefficient values i n subaddress 0x03 to subad - dress 0x09 are correct for the hd color space only. the color components are converted according to the following 1080i and 720p standards (smpte 274m, smpte 296m): r = y + 1.575 pr g = y ? 0.468 pr ? 0.187 pb b = y + 1.855 pb the conversion coefficients should be multiplied by 315 before being written to the ed/hd csc matrix registers . this is reflected in the default values for gy = 0x13b, gu = 0x03b, gv = 0x093, bu = 0x248, and rv = 0x1f0 . if the ed/hd manual csc matrix adjust feature is enabled and anoth er input standard (such as ed) is used, the scale values for gy, gu, gv, bu, and rv must be adjusted according to this input standard color space. the user should consider that the color c omponent conversion may use different scale values. for example, smpte 293m uses the following conversion: r = y + 1.402 pr g = y C 0.714 pr C 0.344 pb b = y + 1.773 pb the programmable csc matrix is used for external ed/hd pixel data and is not functional wh en internal test patterns are enabled. programming the csc matrix if custom manipulation of the ed/hd csc matrix coefficients is required for a ycrcb - to - rgb color space conversion, use the following procedure: 1. enable the ed/hd manual csc matrix adjust fea ture (subaddress 0x02, bit 3). 2. set the output to rgb (subaddress 0x02, bit 5). 3. disable sync on prpb (subaddress 0x35, bit 2). 4. enable sync on rgb (optional) (subaddress 0x02, bit 4). the gy value controls the green signal output level, the bu value contro ls the blue signal output level, and the rv value controls the red signal output level. sd luma and color scale control subaddress 0x9c to subaddress 0x9f when enabled, the sd l uma and c olor s cale c ontrol feature can be used to scale the sd y, cb , and cr output levels. this feature can be enabled using subaddress 0x87, bit 0. t his feature affects all sd output signals, that is, cvbs, y - c, yprpb, and rgb. when enabled, three 10 - bit registers ( sd y scale, sd cb scale, and sd cr s cale) control the scaling of the sd y, cb, and cr output levels. the sd y s cale register contains the scaling factor used to the scale the y level from 0.0 to 1.5 times its initial level. the sd cb scale and sd cr scale registers contain the scaling factors to scale the cb and cr levels from 0.0 to 2.0 times their initial levels, respectively. the values to be written to these 10 - bit registers are calculated using the following equation: y, cb, or cr scal e value = scale factor 512 for example, if scale factor = 1.3 y, cb, or cr scale value = 1.3 512 = 665.6 y, cb, or cr scale value = 666 (rounded to the nearest integer) y, cb, or cr scale value = 1010 0110 10b subaddress 0x9c, sd scale lsb r egiste r = 0x2a subaddress 0x9d, sd y scale r egister = 0xa6 subaddress 0x9e, sd cb s cale r egis ter = 0xa6 subaddress 0x9f, sd cr scale r egister = 0xa6 i t is recommended that the sd luma scale s aturation feature (subaddress 0x87, bit 1) be enabled when scaling the y output level to avoid excessive y output levels . sd hue adjust contro l subaddress 0xa 0 when enabled, the sd hue adjust control register (subaddress 0xa0) is used to adjust the hue on the sd composite and chroma outputs. this feature can be enabled using subaddress 0x87, bit 2. subaddress 0xa0 contains the bits required to vary the hue of t he video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. the ADV7344 provides a range of 22.5 in increments of 0.17578125. for normal operation (zero adjust - me nt), this register is set to 0x80. value 0xff and va lu e 0x00 represent the upper and lower limits, respectively, of the attain - able adjustment in ntsc mode. value 0xff and va lu e 0x01 represent the upper and lower limits, respectively, of the attainable adj ustment in pal mode.
ADV7344 data sheet rev. b | page 60 of 108 the hue adjust value is calculated using the following equation: hue adjust () = 0.17578125 ( hcr d ? 128) where hcr d = hue adjust control register ( decimal ). for example, to adjust the hue by +4, write 0x97 to the hue adjust control register. 97x0151128 17578125.0 4 =+ ? ? ? ? ? ? d where the sum is rounded to the nearest integer. to adjust the hue by ?4, write 0x69 to the hue adjust control register. 96x0105128 17578125.0 4 =+ ? ? ? ? ? ? ? d where the sum is rounded to the nearest integer. sd brightness detect subaddress 0xba the ADV7344 allows monitoring of the brightness level of the incoming video data. the sd brightness detect reg ister (subad - dress 0xba) is a read - only register. sd brightness contro l subaddress 0xa1, bits[6:0] when this feature is enabled, the sd brightness/wss control register (subaddress 0xa1) is used to control brightness by adding a programmable setup level ont o the scaled y data. this feature can be enabled using subaddress 0x87, bit 3. for ntsc with pedestal, the setup can vary from 0 ire to 22.5 ire. for ntsc without pedestal and for pal, the setup can vary from ?7.5 ire to +15 ire. the sd brightness control register is an 8 - bit register. the seven lsbs of this 8 - bit register are used to control the brightness level, which can be a positive or negative value. for example, t o add a +20 ire brightness level to an ntsc signal with pedestal, write 0x28 to subaddre ss 0xa1. 0 (sd brightness value) = 0 ( ire value 2.015631) = 0 (20 2.015631) = 0 (40.31262) 0x28 to a d d a C 7 ire brightness level to a pal signal, write 0x72 to subaddress 0xa1. 0 ( sd brightness value ) = 0 ( ire value 2.075631) = 0 (7 2.015631) = 0x(14.109417) 0001110b 0001110b into twos complem ent = 1110010b = 0x72 table 50 . sample brightness control values 1 setup level (ntsc) with pedestal setup level (ntsc) without pedestal setup level (pal) brightness control value 22.5 ire 15 ire 15 ire 0x1e 15 ire 7.5 ire 7.5 ire 0x0f 7.5 ire 0 ire 0 ire 0x00 0 ire ? 7.5 ire ? 7.5 ire 0x71 1 values in the range of 0x3f to 0x44 may result in an invalid output signal. sd input standard au todetection subaddress 0x87, bit 5 the ADV7344 incl udes an sd input standard autod etect feature. this sd feature can be enabled by s etting subaddress 0x87, bit s[5:1]. when enabled, the ADV7344 can automatically identify an ntsc or a pal b/d/g/h/i input stream. the ADV7344 automatically updates the subcarrier frequency registers with the appropriate value for the identified standard. t he ADV7344 is also configured to correctly encode the identified standard. the sd standard bits (subaddress 0x80, bits[1:0]) and the subcarrier frequency registers are not updated to reflect the identified standard. all registers retain their default or us er - defined values. ntsc without pedestal no setup value added positive setup value added 100 ire 0 ire negative setup value added ?7.5 ire +7.5 ire 06400-069 figure 64 . examples of brightness control values
data sheet ADV7344 rev. b | page 61 of 108 double buffering s ubaddress 0x33, bit 7 for ed/hd; subaddress 0x88, bit 2 for sd double - buffered registers are updated once per field. double buffering im pr oves overall performance because modifications to register settings are not made during active video but take effect prior to the start of the active video on the next field. double buffering can be activated on the following ed/hd registers using subaddre ss 0x33, bit 7: the e d/hd gamma a and gamma b curves and ed/hd cgms registers. double buffering can be activated on the following sd registers using subaddress 0x88, bit 2: the sd gamma a and gamma b curves, sd y scale, sd cr scale, sd cb scale, sd brightn ess, sd closed captioning, and sd macrovision bits[5:0] (subaddress 0xe0, bits[5:0]). programmable dac gai n control subaddress 0x0a to subaddress 0x0b it is possible to adjust the dac output signal gain up or down from its absolute level. this is illustrat ed in figure 65. dac 4 to dac 6 are controlled by register 0x0a. dac 1 to dac 3 are controlled by register 0x0b. case b 700mv 300mv neg a tive gain programmed in dac output leve l registers, subaddress 0x0a, 0x0b case a gain programmed in dac output leve l registers, subaddress 0x0a, 0x0b 700mv 300mv 06399-070 figure 65 . programmable dac gain positive and negative gain in case a of figure 65 , the video output signal is gained. the absolute level of the sync tip and the blanking level increase with respect to the reference video output signal. the overall gain of the signal is increased from the reference signal. in case b of figure 65 , the video output signal is reduced. the absolute level of the sync tip and the blanking level decrease with respect to the reference video output signal. the overall gain of the signal is reduced from the reference signal. the range of this feature is specified for 7.5% of the nominal output from the dacs. for example, if the output current of the dac is 4.33 ma, the dac gain control feature can change this output cu rrent from 4.008 ma (?7.5%) to 4.658 ma (+7.5%). the reset value o f the control registers is 0x00; that is, nominal dac current is output. table 51 shows how the output current of the dacs varies for a nominal 4.33 ma output c urrent. table 51 . dac gain control reg. 0x0a or reg.0x0b dac current (ma) % gain note 0100 0000 (0x40) 4.658 7.5000% 0011 1111 (0x3f) 4.653 7.3820% 0011 1110 (0x3e) 4.648 7.3640% ... ... ... ... ... ... 0000 0010 (0x02) 4.43 0.0360% 0000 0001 (0x01) 4.38 0.0180% 0000 0000 (0x00) 4.33 0.0000% reset value, n ominal 1111 1111 (0xff) 4.25 ?0.0180% 1111 1110 (0xfe) 4.23 ?0.0360% ... ... ... ... ... ... 1100 0010 (0xc2) 4.018 ?7.3640% 1100 0001 (0xc1) 4.013 ?7.3820% 1100 0000 (0xc0) 4.008 ?7.5000% gamma correction subaddress 0x 44 to subaddress 0x57 for ed/hd; subaddress 0xa6 to subaddress 0xb9 for sd generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and output bright - ness level (as perceived on a crt). it can also be applied wherever nonlinear processing is used. gamma correction uses the function signal out = ( signal in ) where i s the gamma correction factor. gamma correction is available for sd and ed/hd video. fo r both variations, there are twenty 8- bit registers. they are used to program the g amma c orrection c urve a and gamma c orrection curve b. ed/hd gamma correcti on is enabled using subaddress 0x35, bit 5. ed/hd gamma c orrection curve a is programmed at subaddress 0x44 to subaddress 0x4d, and ed/hd gamma c orrection curve b is programmed at subaddress 0x4e to subaddress 0x57.
ADV7344 data sheet rev. b | page 62 of 108 sd gamma correction is enabled using su baddress 0x88, bit 6. sd g amma c orrection curve a is programmed at subaddress 0 xa6 to subaddress 0xaf, and sd g amma c orrection curve b is programmed at subaddress 0xb0 to subaddress 0xb9. gamma correction is performed on the luma data only. the user can ch oose one of two correction curves, curve a or curve b. only one of these curves can be used at a time. for ed/hd gamma correction, curve selection is controlled using subaddress 0x35, bit 4. for sd gamma correction, curve selection is controlled using suba ddress 0x88, bit 7. the shape of the gamma correction curve is controlled by defining the curve response at 10 different locations along the curve. by altering the response at these locations, the shape of the gamma correction curve can be modified. betwee n these points, linear interpolation is used to generate intermediate values. considering that the curve has a total length of 256 points, the 10 programmable locations are at the following points : 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. the fol - lo wing locations are fixed and cannot be changed : 0, 16, 240, and 255 . from the curve locations , 16 to 240, the values at the programmable locations and, therefore, the response of the gamma correction curve, should be calculated to produce the following res ult: x desired = (x input ) where: x desired is the desired gamma corrected output. x input is the linear input signal. is gamma correction factor. to program the gamma correction registers, calculate the 10 programmable curve values using the following fo rmula: 16)16240 ( 16240 16 + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = n n where: n is the value to be written into the gamma correction register for point n on the gamma correction curve. n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224. is the gamma correction factor. for example, setting = 0.5 for all programmable curve data points results in the following y n values: y 24 = [(8/224) 0.5 224] + 16 = 58 y 32 = [(16/224) 0.5 224] + 16 = 76 y 48 = [(32/224) 0.5 224] + 16 = 101 y 64 = [(48/224) 0.5 224] + 16 = 120 y 80 = [(64/224) 0.5 224] + 16 = 136 y 96 = [(80/224) 0.5 224] + 16 = 150 y 128 = [(112/224) 0.5 224] + 16 = 174 y 160 = [(144/224) 0.5 224] + 16 = 195 y 192 = [(176/224) 0.5 224] + 16 = 214 y 224 = [(208/224) 0.5 224] + 16 = 232 where the sum of each equation is rounded to the nearest i nteger. the gamma curves in figure 66 and figure 67 are examples only; any user - defined curve in the range from 16 to 240 is acceptable. location 0 0 50 100 150 200 250 300 50 100 150 200 250 0.5 signal input gamma corrected amplitude signal output gamma correction block output to a ramp input 06400-071 figure 66 . signal input (ramp) and signal output for gamma 0.5 location 0 0 50 100 150 200 250 300 50 100 150 200 250 gamma corrected amplitude gamma correction block to a ramp input for various gamma values 0.3 0.5 1.5 1.8 signal input 06400-072 figure 67 . signal input (ramp) and selectable output curves
data sheet ADV7344 rev. b | page 63 of 108 ed/hd sharpness filter and adaptive filt er controls subaddress 0x4; subaddress 0x58 to subaddress 0x5d there are three filter mod es available on the ADV7344, a sharpness filter mode and two adaptive filter modes. ed/hd sharpness filter mode to enhance or attenuate the y signal in the frequency ranges shown in figure 68 , the ed/hd sharpness filter must be en abled (subaddress 0x31, bit 7) and the ed/hd adaptive filter must be disabled (subaddress 0x35, bit 7). to select one of the 256 individual responses, the corresponding gain values, which range from C 8 to +7 for each filter, must be programmed into the ed/ hd sharpness filter gain register at subaddress 0x40. ed/hd adaptive filter mode the ed/hd adaptive f ilter ( threshold a, threshold b, and threshold c) registers, the ed/hd adaptive f ilter ( gain 1, gain 2, and gain 3) registers, and the ed/hd sharpness filt er gain register are used in adaptive filter mode. to activate the adaptive filter control, the ed/hd sharpness filter and the ed/hd adaptive filter must be enabled (subaddress 0x31, bit 7, and subaddress 0x35, bit 7, respectively). the derivative of the incoming signal is compared to the three programmabl e threshold values: ed/hd adaptive f ilter ( threshold a, threshold b, and threshold c ) registers (subaddress 0x5b, subaddress 0x5c, and subaddress 0x5d, respectively). the recommended threshold range is 16 to 235, although any value in the range of 0 to 255 can be used. the edges can then be attenuated with the settings in the ed/hd adaptive f ilter ( gain 1, gain 2, and gain 3) registers (subaddress 0x58, subaddress 0x59 and subaddress 0x5a, respectively), a nd the ed/hd sharpness filter gain register (subaddress 0x40). there are two adaptive filter modes available. the mode is selected using the ed/hd adaptive filter mode control (subaddress 0x35, bit 6) as follows : ? mode a is used when the ed/hd adaptive filter mode control is set to 0. in this case, filter b (lpf) is used in the adaptive filter block. in addition, only the programmed values for gain b in the ed/hd sharpness filter gain register and ed/hd adaptive f ilter ( gain 1, gain 2, and gain 3) registers are applied when needed. the gain a values are fixed and cannot be changed. ? mode b is used when ed/hd adaptive filter mode control is set to 1. in this mode, a cascade of filter a and filter b is used. both settings for gain a and gain b in the ed/hd sharpness filter gain register and ed/hd adaptive f ilter ( gain 1, gain 2, and gain 3) registers become active when needed. frequency (mhz) filter a response (gain ka) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 frequency (mhz) filter b response (gain kb) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 frequency (mhz) magnitude response (linear scale) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 10 12 input signal step frequency response in sharpness filter mode with ka = 3 and kb = 7 sharpness and adaptive filter control block 0 2 4 6 8 06400-073 figure 68 . ed/hd sharpness and adaptive filter control block
ADV7344 data sheet rev. b | page 64 of 108 f e d a b c 1 r4 r2 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 r2 r1 1 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 9.99978ms 9.99978ms 06400-074 figure 69 . ed/ hd sh arpness filter control with different gain settings for ed/hd sharpness filter gain values ed/hd sharpness filter and adaptive filt er application examples sharpness filter application the ed/hd sharpness filter can be used to enhance or attenuate the y v ideo output signal. the register settings in table 52 are used to achieve the results shown in figure 69. input data i s generated by an external signal source. table 52. e d/hd sharpness control settings for figure 69 subaddress register setting reference 1 0x00 0xfc 0x01 0x10 0x02 0x20 0x30 0x00 0x31 0x81 0x40 0x00 a 0x40 0x08 b 0x40 0x04 c 0x40 0x40 d 0x40 0x80 e 0x40 0x22 f 1 see figure 69 . adaptive filter control application the register settings in tabl e 53 are used to obtain the results shown in figure 71 , that is, to remove the r inging on the input y signal, as shown in figure 70 . input data is generated by an external signal source. table 53 . register settings for figure 71 subaddress register se tting 0x00 0xfc 0x01 0x38 0x02 0x20 0x30 0x00 0x31 0x81 0x35 0x80 0x40 0x00 0x58 0xac 0x59 0x9a 0x5a 0x88 0x5b 0x28 0x5c 0x3f 0x5d 0x64
data sheet ADV7344 rev. b | page 65 of 108 06400-075 figure 70 . input signal to ed/hd adaptive filter 06400-076 figure 71 . output signal from ed/hd adaptive filter (mode a) when the adaptive filter mode is changed to mode b (subaddress 0x35, bit 6), the output shown in figure 72 can be obtained. 06400-077 figure 72 . outp ut signal from ed/hd adaptive filter (mode b) sd digital noise reduction subaddress 0xa3 to subaddress 0xa5 digital noise reduction (dnr) is applied to the y data only. a filter block selects the high frequency, low amplitude compo - nents of the incoming s ignal (dnr input select). the absolute value of the filter output is compared to a programmable threshold value (dnr threshold control). there are two dnr modes available, dnr mode and dnr sharpness mode. in dnr mode, if the absolute value of the filter ou tput is smaller than the threshold, it is assumed to be noise. a programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal. in dnr sharpness mode, if the absolute value of the filter output is le ss than the programmed threshold, it is assumed to be n oise. otherwise, if the level e xceeds the threshold, now identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) is added to the original signal to boost high freq uency components and sharpen the video image. in mpeg systems, it is common to process the video information in blocks of 8 pixels 8 pixels for mpeg2 systems or 16 pixels 16 pixels for mpeg1 systems (block size control). dnr can be applied to the resul ting block transition areas that are known to contain noise. generally, the block transition area contains two pixels. it is possible to define this area to contain four pixels (border area). it is also possible to compensate for variable block positioning or differences in ycrcb pixel timing with the use of the dnr block offset. the digital noise reduction registers are three 8 - bit registers. they are used to control the dnr processing. block size control border area block offset coring gain data coring gain border gain dnr control filter output > threshold? input filter block filter output < threshold dnr out + + main signal path add signal above threshold range from original signal dnr sharpness mode noise signal path y data input block size control border area block offset coring gain data coring gain border gain dnr control filter output < threshold? input filter block filter output > threshold dnr out main signal path subtract signal in threshold range from original signal dnr mode noise signal path y data input ? + 06400-078 figure 73 . sd dnr block diagram
ADV7344 data sheet rev. b | page 66 of 108 coring gai n border subaddress 0xa3, bits[3:0] these four bits are assigned to the gain factor applied to border areas. in dnr mode, the range of gain values is 0 to 1 in incre - ments of 1/8. this factor is applied to the dnr filter output that lies below the set thre shold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter output that lies above the threshold range. the result is added to the original signal. coring gain data subaddress 0xa3, bits[7:4] these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode, the range of gain values is 0 to 1 in increments of 1/8. this factor is applied to the dnr filter output that lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter ou tput that lies above the threshold range. the result is added to the original signal. oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo dnr27 to dnr24 = 0x01 offset caused by variations in input timing apply border coring gain apply data coring gain 06400-079 figure 74 . sd dnr offset control dnr threshold subaddress 0xa4, bits[5:0] these six bits are used to define the threshold value in the range of 0 to 63. the range is an absolute value. border area subaddress 0xa4, bit 6 when this bit is set to logic 1, the block transition area can be defined to consist of four pixels. if this bit is set to logic 0, the border transition area consists of two pixe ls, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (n tsc) 8 8 pixel block two-pixel border data 8 8 pixel block 06400-080 figure 75 . sd dnr border area block size control subaddress 0xa4, bit 7 this bit is used to select the size of the data blocks to be processed. setting the block size con trol function to logic 1 defines a 16 pixel 16 pixel data block, and logic 0 defines an 8 pixel 8 pixel data block, where one pixel refers to two clock cycles at 27 mhz. dnr input select control subaddress 0xa5, bits[2:0] three bits are assigned to sel ect the filter, which is applied to the incoming y data. the signal that lies in the pass band of the selected filter is the signal that is dnr processed. figure 76 shows the filter responses selectable with this control. filter c filter b filter a filter d frequency (mhz) 0 0.2 0.4 0.6 magnitude 0.8 1.0 0 1 2 3 4 5 6 06400-081 fig ure 76 . sd dnr input select dnr mode control subaddress 0xa5, bit 3 this bit controls the dnr mode selected. logic 0 selects dnr mode; logic 1 selects dnr sharpness mode. dnr works on the principle of defining low amplitude, high f requency signals as probable noise and subtracting this noise from the original signal. in dnr mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. the threshold is set in dnr register 1. when dnr sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal because this data is assumed to be valid data and not noise. the overall effect is that the signa l is boosted (similar to using the extended ssaf filter). dnr block offset control subaddress 0xa5, bits[7:4] four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. consider the coring gain positions fixed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
data sheet ADV7344 rev. b | page 67 of 108 sd active video edge control subaddress 0x82, bit 7 the ADV7344 is able t o control fast rising and falling signals at the start and end of active video to minimize ringing. when the active video edge control feature is enabled (subaddress 0x82, bit 7 = 1), the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. at the start of active video, the first three pixels are multiplied by 1/8, 1/2, and 7/8, respectively. approaching the end of active video, the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively. all other active video pixels pass through unpro - cessed. 100 ire 0 ire 100 ire 12.5 ire 87.5 ire 0 ire 50 ire luma channel with ac tive video edge disabled luma channel with ac tive video edge e nabl ed 06400-082 figure 77 . example of active video edge functionality volts 0 2 4 f2 l135 6 8 10 12 ire:flt ?50 0 0 50 100 0.5 06400-083 figure 78 . example of video output with subaddress 0x82, bit 7 = 0 volts 0 2 ?2 4 6 8 10 12 f2 l135 ire:flt ?50 0 50 100 0 0.5 06400-084 figure 79 . example of video output with subaddress 0x82, bit 7 = 1
ADV7344 data sheet rev. b | page 68 of 108 external horizontal and verti cal synchronization control for synchronization purposes, the ADV7344 is able to accept either time codes embedded in the input pixel data or external synchronization signals provided on the s_hsync , s_vsync , p_hsync , p_vsync , and p_blank pins (s ee tabl e 54 ). it is also possible to output synchronization signals on the s_hsync and s_vsync pins (see table 55 to table 57). table 54 . timing synchronization signal input options signal pin condition sd hsync in s_hsync sd s lave t iming ( mode 1, mode 2, or mode 3) selected (subaddress 0x8a[2:0]) 1 sd vsync in s_vsync sd s lave t iming (m ode 1, mode 2, or mode 3 ) selected (subaddress 0x8a[2:0]) 1 ed/hd hsync in p_hsync ed/hd t iming sync, in puts enabled (subaddress 0x30, bit 2 = 0) ed/hd vsync in p_vsync ed/hd t iming sync, i nputs enabled (subaddress 0x30, bit 2 = 0) ed/hd blank in p_blank 1 sd and ed/hd timing sync. outputs must also be disabled (subaddress 0x02[7:6] = 00). table 55 . timing synchronization signal output options signal pin condition sd hsync out s_hsync sd t iming s ync , o utputs enabled (subaddr ess 0x02, bit 6 = 1) 1 sd vsync out s_vsync sd t iming s ync , o utputs enabled (subaddress 0x02, bit 6 = 1) 1 ed/hd hsync out s_hsync ed/hd t iming s ync , o utputs enabl ed (subaddress 0x02, bit 7 = 1) ed/hd vsync out s_vsync ed/hd t iming s ync , o utputs enabled (subaddress 0x02, bit 7 = 1) 1 ed/hd timing sync. outputs must also be disabled (subaddress 0x02, bit 7 = 0). table 56. hsync output control 1, 2 ed/hd input sync format ( subaddress 0x30, bit 2) ed/hd hsync control ( subaddress 0x34, bit 1) ed/hd sync output enable ( subaddress 0x02, bit 7) sd sync outpu t enable ( subaddress 0x02, bit 6) signal on s_hsync pin duration x x 0 0 tristate n/a x x 0 1 pipelined sd hsync see sd timing 0 0 1 x pipelined ed/hd hsync a s per hsync timing 1 0 1 x pipelined ed/hd hsync based on av code h bit same as line blanking interval x 1 1 x pipelined ed/hd hsync based on the horizontal counter same as embedded hsync 1 in all ed/hd standards where there is an hsync output, the start of the hsync pulse is aligned with the falling edge of the embedded hsync in the output video . 2 x = dont care. table 57. vsync output control 1, 2 ed/hd input sync format (0x30, bit 2) ed/hd vsync control (0x34, bit 2) ed/hd sync output enable (0x02, bit 7) sd sync output enab le (0x02, bit 6) video standard signal on s_vsync pin duration x x 0 0 x tristate. C x x 0 1 interlaced pipelined sd vsync /field. see sd timing 0 0 1 x x pipelined ed/hd vsync or field signal. as per vsync or field signal timing 1 0 1 x all hd interlaced standards pipelined field signal based on av code f bit. field 1 0 1 x all ed/hd progressive standards pipelined v sync based on av code v bit. vertical blanking interval x 1 1 x all ed/hd standards except 525p pipelined ed/hd vsync based on vertical counter. aligned with serration lines x 1 1 x 525p pipelined ed/hd vsync based on vertical counter. vertical blanking interval 1 in all ed/hd standards where there is a vsync output, the start of the vsync pulse is aligned with the falling edge of the embedded vsync in the outpu t video. 2 x = dont care.
data sheet ADV7344 rev. b | page 69 of 108 low power mode subaddress 0x0d, bits[2:0] for power - sen sitive applications, the ADV7344 s upports an analog devices proprietary low power mode of operation on dac 1, dac 2, and dac 3. to u s e this low power mode, these dacs must be operating in full - drive mode (r set 1 = 510 ? , r l = 37.5 ?). low pow er mode is not available in low - drive mode (r set = 4.12 k ? , r l = 300 ?). low power mode can be independently enabled or disabled on dac 1, dac 2, and dac 3 using subaddress 0x0d, bits[2:0]. low power mode is disabled by default on each dac. in low power mode, dac current consumption is content dependent. on a typical video stream, it can be reduced by as much as 40%. for applications requiring the highest possible video performance, low power mode should be disabled. cable detectio n subaddress 0x10 the ADV7344 includes an analog devices proprietary cable detection feature . the cable detection feature is available on dac 1 and dac 2, while operating in full - drive mode ( r set 1 = 510 ? , r l1 = 37.5 ?, assuming a connected cable). the feature is not available in low - drive mode ( r set 1 = 4.12 k ? , r l = 300 ?). for a dac to be monitored, the dac must be powered up in subaddress 0x00. the cable detection feature can be used with all sd, ed, and hd video standards. it is available for all output configurations, that is, cvbs, yc, yprpb, and rgb output configurations. for cvbs/yc output configurations, both dac 1 and dac 2 are monitored; that is, the cvbs and yc luma outputs are monitored. for yprpb and rgb output configurations, only dac 1 is monitored ; that is, the luma or green output is monitored. once per frame, the ADV7344 monitors dac 1 and/or dac 2, updating subaddress 0x10, bit 0 and bit 1, respectively. if a cable is detected on one of the dacs, the relevant bit is set to 0. if not, the bit is set to 1. dac autop ower - down subaddress 0x10, bit 4 for power - sen sitive applications, a dac auto power - down feature can be enabled using subaddress 0x10, bit 4. this feature is available only when the cable detection feature is enabled. with this feature enabled, the cable detection circuitry monitors dac 1 and/or dac 2 once per frame. if they are unconnected, some or all of the dacs automatically power down. which dac or dacs are powered down depen ds on the selected output configuration. for cvbs/yc output configurations, if dac 1 is unconnected, only dac 1 powers down. if dac 2 is unconnected, dac 2 and dac 3 power down. for yprpb and rgb output configurations, if dac 1 is unconnected, all three da cs power down. dac 2 is not monitored for yprpb and rgb output configurations. once p er frame, dac 1 and/or dac 2 is monitored. if a cable is detected, the appropriate dac or dacs remain powered up for the duration of the frame. if no cable is detected, th e appropriate dac or dacs power down until the next frame when the process is repeated. sleep mode subaddress 0x00, bit 0 in sleep mode, most of the digital i/o pins of the adv7340/ adv7341 are disabled. for inputs, this means that the external data is ign ored, and internally the logic normally driven by a given input is just tied low or high. this includes clkin x. for digital output pins, this means that the pin goes into tristate (high impedance) mode. there are some exceptions to allow the user to contin ue to communicate with the part via i 2 c : the alsb , sda, and scl pins are kept alive. pixel and control po rt readback subaddress 0x12 to subaddress 0x16 the ADV7344 supports the readback of most digital inputs via the i 2 c mpu port. this feature is useful fo r board -level connectivity testing with upstream devices. the pixel port (s[ 9:0], y[9:0] , and c[9:0]) , the control port ( s_ hsync , s_ vsync , p_ hsync , p_vsync , and p_blank ), and the sfl pin are available for readback via the mpu port. the readback registers are located at subaddress 0x1 2 to subaddress 0x16. when using this feature, apply a clock signal to the clkin_a pin to register the levels ap plied to the input pins. reset mechanism subaddress 0x17, bit 1 the ADV7344 has a software reset accessible via the i 2 c mpu port. a software reset is activated by writing a 1 to subaddress 0x17, bit 1. this resets all registers to their default va lues. thi s bit is self - clearing; that is, after a 1 has been written to the bit, the bit automatically returns to 0. the ADV7344 includes a power - on reset (por) circuit to ensure correct operation after power - up. sd teletext insertio n subaddress 0x c9 to subaddress 0xce the ADV7344 supp orts the insertion of t eletext data, using a 2- pin interface, when operating in pal mode. teletext insertion is enabled using subaddress 0xc9, bit 0. in accordance with the pal wst teletext standard, t eletext data should be inserted i nto the ADV7344 at a rate of 6.9375 mbps. the t eletext data can be inserted on the s_vsync , p _vsync ,
ADV7344 data sheet rev. b | page 70 of 108 or c0 pin. the pin on which the t eletext data is inserted is selected using subaddress 0xc9, bits [3:2]. when t eletext insertion is enabled, a t eletext request signal is output fro m the ADV7344 to indicate when t eletex t data should be inserted. the t eletext request signal is output on the sfl pin. the position (relative to the t eletext data) and width of the request signal are configurable using subaddress 0xca. the request signal can operate in either a line or bit mode. the request signal mode is controlled using subaddress 0xc9, bit 1. to account for the non in teger relationship between the t eletext insertion rate (6.9375 mbps) and the p ixel clock (27 mhz), a t eletext insertion protocol is implemented in the ADV7344. at a rate of 6.9375 mbps, the time taken for the insertion of 37 t eletext bits equates to 144 pixel clock cy cles (at 27 mhz). for every 37 t eletext bits inse rted into the ADV7344, the 10 th , 19 th , 28 th , and 37 th bits are carried for three pixel clock cycles , and the remainder are carried for four pixel clock cycles (totalin g 144 pixel clock cycles). the t eletext inser tion protocol repeats every 37 t eletext bits or 144 pixel clock cycles until all 360 t eletext bits are inserted. 06400-143 address and data run-in clock teletext vbi line 45 bytes (360 bits) ? pal figure 80 . teletext vbi line 06400-144 programmable pulse edges t pd t pd cvbs/y hsync ttx data t synttxout 10.2 s ttx del ttx st t synttxout = 10.2s. t pd = pipeline delay through ADV7344. ttx del = ttx req to ttx data (programmable range = 4 bits [0 to 15 pixel clock cycles]). ttx req figure 81 . teletext functionality diagram
data sheet ADV7344 rev. b | page 71 of 108 printed circuit boar d layout and design unused pins if the s_hsync , s_vsync , p_hsync , and p_vsync pins are not used, they should be tied to v dd_io through a pull - up resistor (10 k or 4.7 k ). any other unused digital inputs should be tied to ground. unused digital output pins should be left floating. dac outputs can be either left floating or connected to gnd. disabling these outputs is recommended. dac configurations the ADV7344 contains six dacs. all six dacs can be confi gured to operate in low - drive mode. low - drive mode is defined as 4.33 ma full - scale current into a 300 ? load, r l . dac 1, dac 2, and dac 3 can also be configured to operate in full - drive mode. full - drive mode is defined as 34.7 ma full - scale current into a 37.5 ? load, r l . full drive is the recommended mode of operation for dac 1, dac 2, and dac 3 . the adv7 344 contains two r set pins. a resistor connected between the r set1 pin and agnd is used to control the full - scale output current and, therefore, the dac output voltage levels of dac 1, dac 2, and dac 3. for low - drive operation , r set1 must have a value of 4 .12 k?, and r l must have a value of 300 ?. for full - drive operation, r set1 must have a value of 510 ? , and r l must have a value of 37.5 ?. a resistor connected between the r set2 pin and agnd is used to control the full - scale output current and, therefore, the dac output voltage levels of dac 4, dac 5, and dac 6. r set2 must have a value of 4.12 k?, and r l must have a value of 300 ? (that is, low - drive operation only). the resistors connected to the r set1 and r set2 pin s should have a 1% tolerance. the ADV7344 contains two compensation pins, comp1 and comp2. a 2.2 nf compensation capacitor should be connected from each of these pins to v aa . voltage reference the ADV7344 contains an on - chip voltage reference that can be used as a board - level voltage reference vi a the v ref pin. alter - natively, the ADV7344 can be used with an external voltage reference by connecting the reference source to the v ref pin. for optimal performance, an external voltage reference such as the a d1580 should be used with the ADV7344. if an external voltage reference is not used, a 0.1 f capacitor should be connected from the v ref pin to v aa . video output buffer and optional output filter an output buffer is necessary on any dac that operates in low - drive mode (r set x = 4.12 k?, r l = 300 ?). analog devices produces a range of op amps suitable for this application, for example, the ad8061 . for more information about line driver buffering circuits, see the relevant op amp dat a sheet. an optional reconstruction (anti - imaging) low - pass filter (lpf) may be required on the ADV7344 dac outputs if the ADV7344 is connected to a device that requires this filtering. the filter specifications vary with the application. the use of 16 (s d), 8 (ed), or 4 (hd) oversampling can remove the requirement for a reconstruction filter altogether. for applications requiring an output buffer and reconstruction filter, the ada4430 -1 , ada4411 -3 , and ada4410 -6 integrated video filter buffers should be considered. table 58 . ADV7344 output rates input mode ( subaddress 0x01, bits[6:4]) pll co ntrol ( subaddress 0x00, bit 1) output rate (mhz) sd only off 27 (2x) on 216 (16x) ed only off 27 (1x) on 216 (8x) hd only off 74.25 (1x) on 297 (4x) table 59 . output filter requirements application oversampling cutoff frequency (mhz) attenuation C 50 db at (mhz) sd 2 >6.5 20.5 sd 16 >6.5 209.5 ed 1 >12.5 14.5 ed 8 >12.5 203.5 hd 1 >30 44.25 hd 4 >30 267 560 ? 600 ? 22p f 600 ? dac output 75 ? bnc output 10 h 560 ? 3 4 1 06400-085 figure 82 . example of output filter for sd, 16 oversampling 560? 6.8pf 600? 6.8pf 600? dac output 75? bnc output 4.7h 560? 3 4 1 06400-086 figure 83 . example of output filter for ed, 8 oversampling dac output 390nh 33pf 33pf 75 ? 500 ? 300 ? 75? bnc output 500? 3 4 1 3 4 1 06400-087 figure 84 . example of output filter for hd, 4 oversampling
ADV7344 data sheet rev. b | page 72 of 108 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?30 ?60 ?90 ?120 ?150 ?180 ?210 ?240 1m 10m 100m frequency (hz) circuit frequency response 1g group delay (seconds) phase (degrees) magnitude (db) 21n 18n 15n 12n 9n 6n 3n 0 24n gain (db) 06400-088 figure 85 . output filter plot for sd, 16 oversampling 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1m 10m 100m 1g frequency (hz) circuit frequency response magnitude (db) group delay (seconds) phase (degrees) gain (db) 320 240 160 80 0 ?80 ?160 ?240 480 400 14n 12n 10n 8n 6n 4n 2n 0 18n 16n 06400-089 figure 86 . output filter plot for ed, 8 oversampling 0 ?50 1 frequency (mhz) circuit frequency response gain (db) phase (degrees) 10 100 ?10 ?20 ?30 ?40 200 ?200 120 40 ?40 ?120 group delay (seconds) phase (degrees) magnitude (db) 06400-090 figure 87 . output filter plot for hd, 4 oversampling printed circuit boar d (pcb) layout the ADV7344 is a highly integrated circui t containing both precision analog and high speed digital circuitry. it is designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system - level design so that optimal performance is achieved. the layout should be optimized for lowest noise on the ADV7344 power and ground planes by shielding the digital inputs and providing good power supply decoupling. it is recomme nded to use a 4- layer printed circuit board with ground and power planes separating the signal trace layer and the solder side layer. component placement component placement should be carefully considered to separate noisy circuits, such as clock signals a nd high speed digital circuitry , from analog circuitry. the external loop filter components and components connected t o t h e c o m p, v ref , and r set x pins should be placed as close as possible to and on the same side of the pcb as the ADV7344. adding vias to the pcb to get the components closer to the ADV7344 is not recommended. it is recommended that the ADV7344 be placed as close as possible to the output connector, with the dac output traces as short as possible. the termination resistors on the dac output traces should be placed as close as possible to and on the same side of the pcb as the ADV7344. the termination resistors should overlay the pcb ground plane. external filter and buffer components connected to the dac outputs should be placed as close as p ossible to the ADV7344 to minimize the possibility of noise pi ckup from neighboring circuitry and to minimize the effect of trace capacitance on output bandwidth. this is particularly important when operating in low - drive mode (r set x = 4.12 k?, r l = 300 ?). power supplies it is recommended that a separate regulated supply be provided for each power domain (v aa , v dd , v dd_io , and pv dd ). for optimal performance, linear regulators rather than switch mode regulators should be used. if swit ch mode regulators must be used, care must be taken with regard to the quality of the output voltage in terms of ripple and noise. this is particularly true for the v aa and pv dd power domains. each power supply should be individually connected to the syste m power supply at a single point through a suitable filtering device, such as a ferrite bead. power supply decoupling it is recommended that each power supply pin be decoupled with 10 nf and 0.1 f ceramic capacitors. the v aa , pv dd , v dd_io , and both v dd pi ns should be individually decoupled to ground. the decoupling capacitors should be placed as close as possible to the ADV7344 with the capacitor leads kept as short as possible to minimize lead inductance. a 1 f tantalum capacitor is recommended across th e v aa supply in addition to the 10 nf and 0.1 f ceramic capacitors.
data sheet ADV7344 rev. b | page 73 of 108 power supply sequencing if the alsb pin is tied low, a power supply sequence is required for proper operation of the part. the v dd_io power supply must be established a minimum of 250 s prior to the v dd power supply being established. the v aa and pv dd power supplies can be established at any time and in any order. tying alsb to v dd_io completely removes this pss requirement. digital signal interconnect the digital signal traces should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal traces should not overlay the v aa or pv dd power planes. due to the high clock rates used, avoid long clock traces to the ADV7344 to minimize noise pickup. any p ull - up termination resistors for the digital inputs should be connected to the v dd _io power supply. any unused digital inputs should be tied to ground. analog signal interconnect dac output traces should be treated as transmission lines with appropriate me asures taken to ensure optimal performance (for example, impedance matched traces). the dac output traces should be kept as short as possible. the termination resistors on the dac output traces should be placed as close as possible to , and on the same side of the pcb as , the ADV7344. to avoid crosstalk between the dac outputs, it is recom - mended that as much space as possible be left between the traces connected to the dac output pins. adding ground traces between the dac output traces is also recommended.
ADV7344 data sheet rev. b | page 74 of 108 typical application circuit 06400-091 dac 1 dac 1 dac 3 dac1 to dac3 low drive option r set1 agnd 4.12k? 75? agnd 300? ada4411-3 dac 2 lpf dac 2 75? agnd 300? ada4411-3 lpf dac 3 75? agnd 300? ada4411-3 lpf y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 dgnd dgnd pgnd pgnd 0.1f gnd_io 0.01f gnd_io 33f gnd_io 10f gnd_io ferrite bead v dd_io v dd_io power supply decoupling 0.1f pgnd 0.01f pgnd 33f pgnd 10f pgnd ferrite bead pv dd (1.8v) pv dd power supply decoupling 0.1f agnd 0.01f agnd 33f agnd 10f agnd ferrite bead v aa v aa power supply decoupling 0.1f dgnd 0.01f dgnd 33f agnd 10f dgnd ferrite bead v dd (1.8v) v dd power supply decoupling for each power pin v dd_io pv dd v aa v dd ADV7344 1.235v c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 s_hsync s_vsync p_hsync p_vsync p_blank clkin_a clkin_b agnd agnd dgnd dgnd gnd_io gnd_io v ref ad1580 v aa 1.1k? optional. if the internal voltage reference is used, a 0.1f capacitor should be connected from v ref to v aa . 0.1f r set1 r set2 agnd 4.12k? 510? comp1 comp2 v aa 2.2nf v aa 2.2nf ext_lf1 ext_lf2 sda scl alsb pixel port inputs control inputs/outputs clock inputs i2c port dgnd v dd external loop filter loop filter components should be located close to the ext_lf pin and on the same side of the pcb as the ADV7344. agnd 12nf 150nf 170? pv dd 12nf 150nf 170? 1f agnd dac 1 dac 2 dac 3 agnd 75? agnd 75? agnd 75? dac 1 dac 2 dac 3 dac1 to dac3 full drive option optional lpf optional lpf optional lpf dac 4 dac 4 dac 5 dac 5 dac 6 dac 6 notes 1. for optimum performance, external components connected to the comp, r set , v ref and dac output pins should be located close to and on the same side of the pcb as the ADV7344. 2. the i 2 c device address is configurable using the alsb pin: alsb = 0, i 2 c device address = 0xd4 or 0x54 alsb = 1, i 2 c device address = 0xd6 or 0x56 adi recommends to tie alsb to vdd_io. please refer to power supply sequencing section for more information on this. 3. the resistors connected to the r set pins should have a 1% tolerance. 75? agnd 300? ada4411-3 lpf 75? agnd 300? ada4411-3 lpf 75? agnd 300? ada4411-3 lpf tie either low or high (see note 2) figure 88 . ADV7344 typical application circuit
data sheet ADV7344 rev. b | page 75 of 108 copy generation mana gement system sd cgms subaddress 0x99 to subaddress 0x9b the adv73 44 support s a copy generation management system (cgms) conformin g to the eiaj cpr - 1204 and arib tr - b15 standards. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. subaddress 0x99, bits[6:5] control whether cgms data is output on odd or even fields or both . sd cgms data can only be tra nsmitted when the ADV7344 is configured in ntsc mode. the cgms data is 20 bits long. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit (see figure 89). ed cgms subaddress 0x41 to subaddress 0x43 ; subaddress 0x5e to subaddress 0x6e 525p mode the adv73 44 support s a copy generation management system (cgms) in 525p mo de in accordance with eiaj cpr - 1204- 1. when ed cgms is enabled (subaddress 0x32, bit 6 = 1), 52 5p cgms data is inserted on line 41. the 525p cgms data registers are at subaddress 0x41, subaddress 0x42, and subaddress 0x43. the adv73 44 also support s cgms type b packets in 525p mode in accordance with cea- 805 -a. when ed cgms type b is enabled (subaddress 0x5e, bit 0 = 1), 525p cgms type b data is inserted on line 40. the 525p cgms type b data registers are at subaddress 0x5e to subaddress 0x6e. 625p mode the adv73 44 support s a copy generat ion management system (cgms) in 625p mode in accordance with iec62375 (2004). when ed cgms is enabled (subaddress 0x32, bit 6 = 1), 625p cgms data is inserted on line 43. the 625p cgms data registers are at subaddress 0x42 and subaddress 0x43. hd cgms subaddress 0x41 to subaddress 0x43 ; subaddress 0x5e to subaddress 0x6e the adv73 44 support s a c opy generation management system (cgms) in hd mode (720p and 1080i) in accordance with eiaj cpr - 1204 - 2. when hd cgms is enabled (subaddress 0x32, bit 6 = 1), 720p cgms data is applied to line 24 of the luminance vertical blanking interval. when hd cgms is enabled (subaddress 0x32, bit 6 = 1), 10 80i cgms data is applied to line 19 and line 582 of the luminance vertical blanking interval. the hd cgms data registers are at subaddress 0x41, subad - dress 0x42, and subaddress 0x43. the adv73 44 also support s cgms t ype b packets in hd mode (720p and 1080i) in acco rdance with cea - 805- a. when hd cgms type b is enabled (subaddress 0x5e, bit 0 = 1), 720p cgms data is applied to line 23 of the luminance vertical blanking interval. when hd cgms type b is enabled (subaddres s 0x5e, bit 0 = 1), 1080i cgms data is applied to line 1 8 and line 58 1 of the luminance vertical blanking interval. the hd cgms type b data registers are at subaddress 0x 5e to subaddress 0x 6e . cgms crc functionali ty if sd cgms crc (subaddress 0x99, bit 4) or ed/hd cgms crc (subaddress 0x32, bit 7) is enabled, the upper six cgms data bits, c19 to c14, which comprise the 6 - bit crc check sequence, are automatically calculated on the adv73 44 . this calculation is based on the lower 14 bits (c13 to c0) of the dat a in the cgms data registers , and the result is output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if sd cgms crc or ed/ hd cgms crc is disabled, all 20 bits (c19 to c0) are output directly from the cgms registers (crc must be ca lculated by the user manually). if ed /hd cgms type b crc (subaddress 0x 5e , bit 1 ) is enabled, the upper six cgms type b data bits (p 1 22 to p1 27) tha t compris e the 6 - bit crc check sequence are automatically calculated on the adv73 44 . this calculation is based on the lower 128 bits (h0 to h5 and p0 to p121 ) of the data in the cgms type b data registers. the result is output with the remaining 1 28 bits t o form the complete 134 bits of the cgms type b data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if ed/hd cgms type b crc is disabled, all 134 bits ( h0 to h5 and p0 to p127 ) are output directly from the cgms type b registers (crc must be calculated by the user manually).
ADV7344 data sheet rev. b | page 76 of 108 crc sequence ref 0 ire ?40 ire +70 ire +100 ire 11.2 s 2.235 s 20ns 49.1 s 0.5 s c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 06400-092 figure 89 . standard definition cgms waveform c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 crc sequence ref 5.8 s 0.15 s 6t 0mv ?300mv 70% 10% t = 1/( f h 33) = 963ns f h = horizontal scan frequency t 30ns +700mv 21.2 s 0.22 s 22t c13 c14 c15 c16 c17 c18 c19 bit 1 bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit 20 06400-093 figure 90 . enhanced definition ( 525p ) cgms waveform r s c0 lsb c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 msb peak white sync level 500mv 25mv 5.5 s 0.125 s r = run-in s = start code 13.7 s 06400-094 figure 91 . enhanced definition ( 625p ) cgms waveform crc sequence ref 4t 3.128 s 90ns 17.2 s 160ns 22t t = 1/( f h 1650/58) = 781.93ns f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% +700mv c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 bit 1 bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit 20 06400-095 figure 92 . high definition ( 720p ) cgms waveform
data sheet ADV7344 rev. b | page 77 of 108 crc sequence ref 4t 4.15 s 60ns 22.84 s 210ns 22t t = 1/(f h 2200/77) = 1.038 s f h = horizon tal scan frequenc y 1h t 30ns 0mv ?300mv 70% 10% +700mv c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 bit 1 bit 2 06400-096 bit 20 figure 93 . high definition ( 1080i ) cgms waveform bit 1 bit 2 bit 134 h0 h1 h2 h3 h4 h5 p0 p1 p2 p3 p4 crc sequence 0mv ?300mv +700mv . p122 p123 p124 p125 p126 p127 start .. 70% 10% please referto the cea-805-a specification for timing information 06400-097 figure 94 . enh anced definition (525p) cgms type b waveform 0mv ?300mv +700mv 70% 10% please refer to the cea-805-a specification for timing information bit 1 bit 2 bit 134 h0 h1 h2 h3 h4 h5 p0 p1 p2 p3 p4 crc sequence . p122 p123 p124 p125 p126 p127 .. start 06400-098 figure 95 . high definition (720p and 1080i) cgms type b waveform
ADV7344 data sheet rev. b | page 78 of 108 sd wide screen signa ling subaddress 0 x 99, subaddress 0 x 9a, subaddress 0 x 9b the ADV7344 support s wide screen signali ng (wss) conform - ing to the etsi 300 294 standard. wss data is transmitted on line 23. wss data can be transmitted when the device is configured in pal mode. the wss data is 14 bits long . t he function of each of these bits is shown in table 60 . the wss data is preceded by a run - in sequence and a start code (see figure 96 ). the latter portion of line 23 ( after 42.5 s from the falling edge of hsync ) is available for the insertion of video. wss data transmission on line 23 can be enabled using subaddress 0x99, bit 7 . it is possible to blank the wss portion of line 23 with subaddress 0xa1, bit 7. table 60 . function of wss bit number bit description 13 12 11 10 9 8 7 6 5 4 3 2 1 0 setting aspect ratio, format, position 1 0 0 0 4:3, full format, n/a 0 0 0 1 14:9, letterbox, center 0 0 1 0 14:9, letterbox, top 1 0 1 1 16:9, letterbox, center 0 1 0 0 16:9, letterbox, top 1 1 0 1 >16:9, letterbox, center 1 1 1 0 14:9, full format, center 0 1 1 1 16:0, n/a, n/a mode 0 camera mode 1 film mode color encoding 0 normal pal 1 motion adaptive colorplus helper signals 0 not present 1 present reserved 0 n/a teletext subtitles 0 no 1 yes open subtitles 0 0 no 0 1 subtitles in active image area 1 0 subtitles out of active image area 1 1 reserved surround sound 0 no 1 yes copyright 0 no copyright asserted or unknown 1 copyright asserted copy protection 0 copying not restricted 1 copying restricted active video run-in sequence start code 500mv 11.0 s 38.4 s 42.5 s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w 10 w11 w12 w13 06400-099 figure 96 . wss waveform diagram
data sheet ADV7344 rev. b | page 79 of 108 sd closed captioning subaddress 0 x 91 to suba d dress 0 x 94 the ADV7344 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of the even fields. close d captioning consists of a seven - cycle sinusoid al burst that is frequency - and phase - locked to the caption data. after the clock run - in signal, the blanking level is held for two data bits and is followed by the logic 1 start bit. sixteen bits of data follow the start bit. these consist of two 8 - bit by tes, seven data bits, and one odd parity bit. the data for these bytes is stored in the sd closed captioning registers (subaddress 0x93 to subaddress 0x94). the ADV7344 also supports th e extended closed captioning op eration, which is active dur ing even fields and encoded on s can line 284. the data for this operation is stored in the sd closed captioning registers (subaddress 0x91 to subaddress 0x92). the ADV7344 automatically generates all clock run - in signals and timing that support closed captioning on line 21 and line 284. all pixels inputs are ignored on line 21 and line 284 if closed captioning is enabled. the fcc code of federal regulations (cfr) 47 section 15.119 and eia - 608 describe the closed captioning information for line 21 and line 284. the adv 7344 uses a single buffering method. this means that the closed captioning buffer is only 1 - byte deep. therefore, there is no frame delay in outputting the closed captioning data, unlike other 2 - byte deep buffering systems. the data must be loaded one lin e before it is output on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, whic h in turn loads the new data (two bytes) in every field. if no new data is required for trans mis sion, 0s must be inserted in both data registers; this is called nulling. it is also important to load control codes, all of which are double bytes, on line 21. otherwise, a tv does not recognize them. if there is a message such as hello world that h as an odd number of characters, it is important to add a blank character at the end to make sure that the end - of - caption, 2- byte control code lands in the same field. d0 to d6 d0 to d6 10.5 0.25 s 12.91 s 7 cycles of 0.5035mhz clock run-in reference color burst (9 cycles) frequency = f sc = 3.579545mhz amplitude = 40 ire 50 ire 40 ire 10.003 s 27.382 s 33.764 s byte 1 byte 0 two 7-bit + parity ascii characters (data) s t a r t p a r i t y p a r i t y 06400-100 figure 97 . sd closed captioning waveform, ntsc
ADV7344 data sheet rev. b | page 80 of 108 internal te st pattern generatio n sd test patterns the ADV7344 is able to internally generate sd color bar and black bar test patterns. for this function, a 27 mhz clock signal must be applied to the clkin_a pin. the register settings in tabl e 61 are used to generate an sd ntsc 75% color bar test pattern. cvbs output is available on dac 4, s -v ideo (y - c) output is on dac 5 and dac 6, and yprpb output is on dac 1 to dac 3. o n power - up, the subcarrier frequency registers default to the appro priate values for ntsc. all other registers are set as normal/default. table 61 . sd ntsc color bar test pattern register writes subaddress setting 0x00 0xfc 0x82 0xc9 0x84 0x40 to generate an sd ntsc black bar test pattern, the settings shown in table 61 should be used with an additional write of 0x24 to subaddress 0x02. for pal output of either test pattern, the same settings are used, except that subaddress 0x80 is programmed to 0x11 , and the subc arrier frequency registers are programmed as shown in table 62 . table 62 . pal f sc register writes subaddress description setting 0x8c f sc 0 0xcb 0x8d f sc 1 0x8a 0x8e f sc 2 0x09 0x8f f sc 3 0x2a note th at , when programming the f sc registers, the user must write the values in the sequence f sc 0, f sc 1, f sc 2, f sc 3. the full f sc value to be written is accepted only after the f sc 3 write is complete. ed/hd test patterns the ADV7344 is able to internally gener ate ed/hd black bar and hatch test patterns. for ed test patterns, a 27 mhz clock signal must be applied to the clkin_a pin. for hd test patterns, a 74.25 mhz clock signal must be applied to the clkin_a pin. the register settings in tabl e 63 are used to generate an ed 525p hatch test pattern. yprpb output is available on dac 1 to dac 3. all other registers are set as normal/default. table 63 . ed 525p hatch test pattern register writes subaddress setting 0x00 0x1c 0x01 0x10 0x31 0x05 to generate an ed 525p black bar test pattern, the settings shown in table 63 should be used with an additional write of 0x24 to subaddress 0x02. to generate an ed 525p flat field test patter n, the settings shown in table 63 should be used, except that 0x0d should be written to subaddress 0x31. the y, cr, and cb levels for the hatch and flat field test patterns can be controlled using subaddress 0x36, subaddress 0 x37, and subaddress 0x38, respectively. for ed/hd standards other than 525p, the settings shown in table 63 (and subsequent comments) are used , except that subaddress 0x30, bits[7:3] are updated as appropriate.
data sheet ADV7344 rev. b | page 81 of 108 sd timing mo de 0 (ccir - 656) slave option ( subaddress 0x8a = x x x x x 0 0 0) the ADV7344 is controlled by the sav (start of active video) and eav (end of active video) time codes embedded in the pixel d ata. all timing information is transmitted using a 4 - byte synchron ization pattern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. if the s_vsync and s_hsync pins are not used, they should be tied to v dd_io during th is mode. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y 06400-101 figure 98 . sd slave mode 0 mode 0 (ccir - 656) master option ( subaddress 0x8a = x x x x x 0 0 1) the ADV7344 generates h and f signals required for the sav and eav time codes in the ccir656 standard. the h bit is output o n s_hsync and the f bit is output on s_vsync . 522 523 524 525 8 9 10 11 20 21 22 display display vertical blank odd field even field h f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h f 765 4 32 1 06400-102 figure 99 . sd master mode 0, ntsc
ADV7344 data sheet rev. b | page 82 of 108 622 623 624 625 21 22 23 display display vertical blank h f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h f odd field even field 313 7 6 5 4 32 1 06400-103 figure 100 . sd master mode 0, pal analog video h f 06400-104 figure 101 . s d master mode 0, data transitions mode 1 slave option ( subaddress 0x8a = x x x x x 0 1 0) in this mode, the ADV7344 accepts horizontal sync and odd/even field signals. when hsync is low, a transition of the field input indicates a n ew frame, that is, vertical retrace. the ADV7344 automatically blanks all normally blank lines as required by the ccir- 624 standard . hsync and field are input on the s_hsync and s_vsync p ins, respectively. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 5 9 10 11 20 21 22 display display vertical blank odd field even field field field hsync hsync 7 6 4 3 2 1 8 06400-105 figure 102 . sd slave mode 1, ntsc
data sheet ADV7344 rev. b | page 83 of 108 622 623 624 625 21 22 23 display vertical blank odd field even field field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 field 5 7 6 4 3 2 1 hsy nc hsync 06400-106 figure 103 . sd slave mode 1, pal mode 1 master option ( subaddress 0x8a = x x x x x 0 1 1) in this mode, the ADV7344 can generate horizontal sync and odd/even field signals. when hsync is low, a transition of the field input indicates a new frame, that is, vertical retrace. the ADV7344 automatically blanks all normally blank lines as required by the ccir- 624 standard . pixel data is latched on the rising clock edge following the timing signal transitions. hsync and field are output on the s_hsync and s_vsync pins, respectively. field pixel data cb y cr y hsync pal = 132 clock/2 ntsc = 122 clock/2 06400-107 figure 104 . sd timing mode 1, odd/even field transitions (master/slave) mode 2 slave option ( subaddress 0x8a = x x x x x 1 0 0) in this mode, the ADV7344 accepts horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the ADV7344 automatically blanks all normally blan k lines as required by the ccir- 624 standard . hsync and vsync are input on the s_hsync and s_vsync pins, respectively.
ADV7344 data sheet rev. b | page 84 of 108 522 523 524 525 9 10 11 20 21 22 display display vertical blank odd field even field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 5 7 6 4 3 2 1 8 hsync vsync hsync vsync 06400-108 figure 105 . sd slave mode 2, ntsc 622 623 624 625 21 22 23 display vertical blank odd field even field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 765 4 32 1 hsync vsync hsync vsync 06400-109 figure 106 . sd slave mode 2, pal mode 2 master option ( subaddress 0x8a = x x x x x 1 0 1) in this mode, the ADV7344 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indic ates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the ADV7344 automatically blanks all normally blank lines as required by the ccir- 624 standard . hsync and vsync are output on the s_hsync and s_vsync pins, respectively. cb y pixel data hsync vsync pal = 132 clock/2 ntsc = 122 clock/2 y cr 06400-110 figure 107 . sd timing mode 2, even - to - odd field transition (master/slave)
data sheet ADV7344 rev. b | page 85 of 108 cb pixel data hsync vsync pal = 132 clock/2 ntsc = 122 clock/2 pal = 864 clock/2 ntsc = 858 clock/2 cb y y cr 06400-111 figure 108 . sd timing mode 2 , odd- to - even field transition (master/slave) mode 3 master/slave option ( subaddress 0x8a = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the ADV7344 accepts or generates horizontal sync and odd/even field signals. when hsync is high, a transition of the field input indicates a new frame, that is, vertical retrace. the ADV7344 automatically blanks all normally blank lines as required by the ccir- 624 standard . hsync and vsync are output in master mode and input in slave mode on the s_vsync and s_vsync pins, respe ctively. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 9 10 11 20 21 22 display display vertical blank odd field even field hsync field hsync field 8 765 4 32 1 06400-112 figure 109 . sd timing mode 3, ntsc 622 623 624 625 5 6 21 22 23 display vertical blank odd field even field field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field field display 320 4 32 1 7 hsync hsync 06400-113 figure 110 . sd timing mode 3, pal
ADV7344 data sheet rev. b | page 86 of 108 hd timing vertical blanking interval display 1124 1125 1 2 5 6 7 8 21 43 20 22 560 field 1 field 2 vertical blanking interval display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 p_hsync p_vsync p_hsync p_vsync 06400-114 figure 111 . 1080i hsync and vsync inpu t timing
data sheet ADV7344 rev. b | page 87 of 108 video output levels sd yp rpb output levels smpte/ebu n10 pattern: 100% color bars 300mv 700mv white yellow cyan green magenta red blue black 06400-115 figure 112 . y levels ntsc white yellow cyan green magenta red blue black 700mv 06400-116 figure 113 . pr levels ntsc white yellow cyan green magenta red blue black 700mv 06400-117 figure 114 . pb levels ntsc 700mv 300mv white yellow cyan green magenta red blue black 06400-118 figure 115 . y levels pal white yellow cyan green magenta red blue black 700mv 06400-119 figure 116 . pr levels pal white yellow cyan green magenta red blue black 700mv 06400-120 figure 117 . pb levels pal
ADV7344 data sheet rev. b | page 88 of 108 ed/hd yprpb output l evels input code 940 64 eia-770.2, standard for y output voltage 300mv 700mv 700mv 960 64 eia-770.2, standard for pr/pb output voltage 512 06400-121 figure 118 . eia - 770.2 standard output s ignals (525p/625p) 782mv 714mv 286mv 700mv input code 940 64 eia-770.1, standard for y output voltage 960 64 eia-770.1, standard for pr/pb output voltage 512 06400-122 figure 119 . eia - 770.1 standard output signals (525p/625p) 300mv input code 940 64 eia-770.3, standard for y output voltage 700mv 700mv 600mv 960 64 eia-770.3, standard for pr/pb output voltage 512 06400-123 figure 120 . eia - 770.3 standard output signals (1080i/720p) 300mv 300mv 700mv 700mv input code 1023 64 y?output levels for full input selection output voltage 1023 64 pr/pb?output levels for full input selection output voltage input code 06400-124 figure 121 . output levels for full i nput selection
data sheet ADV7344 rev. b | page 89 of 108 sd/ed/hd rgb output levels pattern: 100%/75% color bars 700mv/525mv 700mv/525mv 700mv/525mv 300mv 300mv 300mv r g b 06400-125 figure 122 . sd/ed rgb output levels rgb sync disabled 700mv/525mv 700mv/525mv 700mv/525mv 300mv r g b 0mv 300mv 0mv 300mv 0mv 06400-126 figure 123 . sd/ed rgb output levels rgb sync enabled 700mv/525mv 700mv/525mv 700mv/525mv 300mv 300mv 300mv r g b 06400-127 figure 124 . hd rgb output levels rgb sync disabled 300mv 0mv 0mv 700mv/525mv 700mv/525mv 700mv/525mv 300mv r g b 600mv 300mv 0mv 600mv 600mv 06400-128 figure 125 . hd rgb output levels rgb sync enabled
ADV7344 data sheet rev. b | page 90 of 108 sd output plots 0.5 0 apl = 44.5% 525 line ntsc slow clamp to 0.00v at 6.72s 10 20 f1 l76 30 40 50 60 100 50 0 ?50 0 volts ire:flt microseconds precision mode off synchronous sync = a frames selected 1, 2 06400-129 figure 126 . ntsc color bars (75%) 0 noise reduction: 15.05db apl = 44.3% 525 line ntsc no filtering slow clamp to 0.00v at 6.72s 10 20 30 40 50 60 microseconds precision mode off synchronous sync = source frames selected 1, 2 f2 l238 50 0 0 ire:flt 0.6 0.4 0.2 0 ?0.2 volts 06400-130 figure 127 . ntsc luma 0 noise reduction: 15.05db apl needs sync source. 525 line ntsc no filtering slow clamp to 0.00 at 6.72 s 10 20 f1 l76 30 40 50 60 50 ?50 0 0.4 0.2 0 ?0.2 ?0.4 precision mode off synchronous sync = b frames selected 1, 2 volts ire:flt microseconds 06400-131 figure 128 . ntsc chroma volts noise reduction: 0.00db apl = 39.1% 625 line ntsc no filtering slow clamp to 0.00 at 6.72 s 10 0 20 l608 30 40 50 60 0.4 0.2 0.6 0 ?0.2 precision mode off synchronous sound-in-sync off frames selected 1, 2, 3, 4 microseconds 06400-132 figure 129 . pal color bars (75%) volts apl needs sync source. 625 line pal no filtering slow clamp to 0.00 at 6.72 s 10 0 20 l575 30 40 50 60 0 0.5 microseconds 70 no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 06400-133 figure 130 . pal luma volts apl needs sync source. 625 line pal no filtering slow clamp to 0.00 at 6.72 s 10 0 20 l575 30 40 50 60 0 0.5 ?0.5 no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 microseconds 06400-134 figure 131 . pal chroma
data sheet ADV7344 rev. b | page 91 of 108 video standards f v h* f f 272t 4t *1 4t 1920t eav code sav code digital active line 4 clock 4 clock 2112 2116 2156 2199 0 44 188 192 2111 0 0 0 0 0 0 0 0 f f f v h* c b c r c r y y fvh* = fvh and parity bits sav/eav: line 1 to 562: f = 0 sav/eav: line 563 to 1125: f = 1 sav/eav: line 1 to 20; 561 to 583; 1124 to 1125: v = 1 sav/eav: line 21 to 560; 584 to 1123: v = 0 for a frame rate of 30hz: 40 samples for a frame rate of 25hz: 480 samples input pixels analog waveform sample number smpte 274m digital horizontal blanking ancillary data (optional) or blanking code 0 h datum 06400-135 figure 132 . eav/sav input data timing diagram (smpte 274m) y eav code ancillary data (optional) sav code digital active line 719 723 736 799 853 0 fvh* = fvh and parity bits s av : line 43 to 525 = 200h sav: line 1 to 42 = 2ac eav: line 43 to 525 = 274h eav: line 1 to 42 = 2d8 4 clock 4 clock 857 719 0 h datum digital horizontal blanking 0 0 0 0 0 0 0 0 c b c r c r y y f v h* smpte 293m input pixels analog waveform sample number f f f f f v h* 06400-136 figure 133 . eav/sav input data timing diagram (smpte 293m) vertical blank 522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 44 active video active video 06400-137 figure 134 . smpte 293m (525p)
ADV7344 data sheet rev. b | page 92 of 108 622 623 624 625 10 11 43 44 45 4 vertical blank active video active video 1 2 5 6 7 8 9 12 13 06400-138 figure 135 . itu- r bt.1358 (625p) 747 748 749 750 26 27 25 744 745 display vertical blanking interval 1 2 3 4 5 6 7 8 06400-139 figure 136 . smpte 296m (720p) display 1124 1125 21 43 20 22 560 field 1 display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 field 2 vertical blanking interval vertical blanking interval 1 2 5 6 7 8 06400-140 figure 137 . smpte 274m (1080i)
data sheet ADV7344 rev. b | page 93 of 108 configuration script s the scripts listed in the following pages can be used to configure the ADV7344 for basic operation. ce rtain features are enabled by default. if required for a specific application, additional features can be enabled. tabl e 64 lists the scripts available for sd modes of operation. similarly, table 85 and table 112 list the scripts available for ed and hd modes of operation, respectively. for all scripts, only the necessary register writes are included. all other registers are assumed to have their default values. standard definitio n table 64. sd configuration scripts input format input data width 1 synchronization format input color space output color space table number 525i (ntsc) 10-b it sdr eav/sav ycrcb yprpb and cvbs/y -c table 65 525i (ntsc) 10-b it sdr hsync / vsync ycrcb yprpb and cvbs/y -c table 66 525i (ntsc) 10-b it sdr eav/sav ycrcb rgb and cvbs/y -c table 67 525i (ntsc) 10-b it sdr hsync / vsync ycrcb rgb and cvbs/y -c table 68 525i (ntsc) 20-b it sdr hsync / vsync ycrcb yprpb and cvbs/y -c table 69 525i (ntsc) 20-b it sdr hsync / vsync ycrcb rgb and cvbs/y -c table 70 525i (ntsc) 30-b it sdr hsync / vsync rgb yprpb and cvbs/y -c table 71 525i (ntsc) 30-b it sdr hsync / vsync rgb rgb and cvbs/y -c table 72 ntsc sq. pixel 10 - b it sdr eav/sav ycrcb cvbs/y - c (s - video) table 73 ntsc sq. pixel 30-b it sdr hsync / vsync rgb cvbs/y - c (s - video) table 74 625i (pal) 10-b it sdr eav/sav ycrcb yprpb and cvbs/y -c table 75 625i (pal) 10-b it sdr hsync / vsync ycrcb yprpb and cvbs/y -c t able 76 625i (pal) 10-b it sdr eav/sav ycrcb rgb and cvbs/y -c table 77 625i (pal) 10-b it sdr hsync / vsync ycrcb rgb and cvbs/y -c table 78 625i (pal) 20-b it sdr hsync / vsync ycrcb yprpb and cvbs/y -c table 79 625i (pal) 20 - b it sdr hsync / vsync ycrcb rgb and cvbs/y - c table 80 625i (pal) 30-b it sdr hsync / vsync rgb yprpb and cvbs/y -c table 81 625i (pal) 30-b it sdr hsync / vsync rgb rgb and cvbs/y -c table 82 pal sq. pixel 10-b it sdr eav/sav ycrcb cvbs/y - c (s - video) table 83 pal sq. pixel 30-b it sdr hsync / vsync rgb cvbs/y - c (s - video) table 84 1 sdr = single data rate table 65 . 10 - bit 525i ycrcb in (eav/sav), yprpb and cvbs/y -c out subaddress setting description 0x17 0x02 s oftware reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc9 pixel data valid. yprpb and cvbs/y -c out. ssaf prpb filter enabled. activ e video edge control enabled. pedestal enabled. 0x88 0x10 10- bit input enabled. table 66 . 10 - bit 525i ycrcb in, yprpb and cvbs/y -c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll e nabled (16). 0x01 0x00 sd input mode. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc9 pixel data valid. yprpb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. pedestal enabled. 0x88 0x10 10- bit input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization.
ADV7344 data sheet rev. b | page 94 of 108 table 67 . 10 - bit 525i ycrcb in (eav/sav), rgb and cvbs/y -c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc9 pixel data valid. rgb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. pedestal enabled. 0x88 0x10 10- bit input enabled. table 68. 10 - bit 525i ycrcb in, rgb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc 9 pixel data valid. rgb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. pedestal enabled. 0x88 0x10 10- bit input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchroniz ation. table 69. 20 - bit 525i ycrcb in, yprpb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc9 pixel data valid. yprpb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. pedestal enabled. 0x88 0x18 20- bit input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. table 70. 20 - bit 525i ycrcb in, rgb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc9 pixel data valid. rgb and cvbs/y -c out. ssaf prpb filter enabled. active video edge c ontrol enabled. pedestal enabled. 0x88 0x18 20- bit input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. table 71. 30 - bit 525i rgb in, yprpb and cvbs/y - c out su baddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc9 pixel data valid. yprpb and cvb s/y -c out. ssaf prpb filter enabled. active video edge control enabled. pedestal enabled. 0x87 0x80 rgb input enabled. 0x88 0x10 10- bit input enabled (10 3 = 30 - bit). 0x8a 0x0c timing mode 2 (s lave). hsync / vs ync synchronization. table 72. 30 - bit 525i rgb in, rgb and cvbs/y -c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output e nabled. rgb output sync enabled. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc9 pixel data valid. rgb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. pedestal enabled. 0x87 0x80 rgb input enabled. 0x88 0x10 10- bit input enabled (10 3 = 30 - bit). 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization.
data sheet ADV7344 rev. b | page 95 of 108 table 73. 10 - bit ntsc square pixel ycrcb in (eav/sa v), cvbs/y - c out subaddress setting description 0x17 0x02 software reset 0x00 0x1c all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xdb pixel data va lid. cvbs/y - c (s - video) out. ssaf prpb filter enabled. active video edge control ena bled. pedestal enabled. square p ixel m ode enabled. 0x88 0x10 10- bit ycbcr input enabled. 0x8c 0x55 subcarrier frequency register values for cvbs and/or s - video (y - c) output in ntsc s quare p ixel m ode (24.5454 mhz input clock). 0x8d 0x55 0x8e 0x55 0x8f 0x25 table 74. 30 - bit ntsc square pixel rgb in, cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs ena bled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x10 ntsc standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xdb pixel data valid. cvbs/y - c (s - video) out. ssaf prpb filter enabled. active video edge control enabled. pedestal enabled. square p ixel m ode enabled. 0x87 0x80 rgb input enabled. 0x88 0x10 30- bit rgb input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. 0x8c 0x55 subcarrier frequency register va lues for cvbs and/or s - vid eo (y - c) output in ntsc square p ixel m ode (24.5454 mhz input clock). 0x8d 0x55 0x8e 0x55 0x8f 0x25 table 75. 10 - bit 625i ycrcb in (eav/sav), yprpb and cvbs/y - c out subaddress setting description 0 x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc1 pixel data valid. yprpb and cvbs/y -c out. ssaf prpb filter enabl ed. active video edge control enabled. 0x88 0x10 10- bit input enabled. t able 76. 10 - bit 625i ycrcb in, yprpb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (1 6). 0x01 0x00 sd input mode. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc1 pixel data valid. yprpb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. 0x88 0x10 10- bit input enabl ed. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. table 77. 10 - bit 625i ycrcb in (eav/sav), rgb and cvbs/y - c out subaddress setting description 0x17 0x02 software res et. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc1 pixel data valid. rgb and cvb s/y -c out. ssaf prpb filter enabled. active video edge control enabled. 0x88 0x10 10- bit input enabled. table 78. 10 - bit 625i ycrcb in, rgb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc al l dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc1 pixel data valid. rgb and cvbs/y -c out. ssaf p rpb filter enabled. active video edge control enabled. 0x88 0x10 10- bit input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization.
ADV7344 data sheet rev. b | page 96 of 108 table 79. 20 - bit 625i ycrcb in, yp rpb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc1 pixel dat a valid. yprpb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. 0x88 0x18 20- bit input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. table 80. 20 - bit 625i ycrcb in, rgb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x80 0x1 1 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc1 pixel data valid. rgb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. 0x88 0x18 20- bit input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. table 81. 30 - bit 625i rgb in, yprpb and cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xc1 pixel data valid. yprpb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. 0x87 0x80 rgb input enabled. 0x8 8 0x10 10- bit input enabled (10 3 = 30 - bit). 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. table 82. 30 - bit 625i rgb in, rgb and cvbs/y - c out subaddress setting de scription 0x17 0x02 software reset. 0x00 0xfc all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0 xc1 pixel data valid. rgb and cvbs/y -c out. ssaf prpb filter enabled. active video edge control enabled. 0x87 0x80 rgb input enabled. 0x88 0x10 10- bit input enabled (10 3 = 30 - bit). 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. table 83. 10 - bit pal square pixel ycrcb in (eav/sav), cvbs/y - c out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (16). 0x01 0x00 sd inpu t mode. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xd3 pixel data valid. cvbs/y - c (s - video) out. ssaf prpb filter enabled. active video edge control enabled. square pixel m ode enabled. 0x88 0x10 10 - bit ycbcr i nput enabled. 0x8c 0x0c subcarrier frequency register values for cvbs and/or s - video (y - c) output in pal s quare p ixel m ode (29.5 mhz input clock). 0x8d 0x8c 0x8e 0x79 0x8f 0x26 table 84. 30 - bit pal square pixel rgb in, cvbs/y- c out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (16). 0x01 0x00 sd input mode. 0x80 0x11 pal standard. ssaf luma filter enabled. 1.3 mhz chroma filter enabled. 0x82 0xd3 pixel data valid. cvbs /y - c (s - video) out. ssaf prpb filter enabled. active video edge control enabled. square pixel m ode enabled. 0x87 0x80 rgb input enabled. 0x88 0x10 30- bit rgb input enabled. 0x8a 0x0c timing mode 2 (s lave). hsync / vsync synchronization. 0x8c 0x0c subcarrier frequency register values for cvbs and/or s - video (y - c) output in pal s quare p ixel m ode (29.5 mhz input clock). 0x8d 0x8c 0x8e 0x79 0x8f 0x26
data sheet ADV7344 rev. b | page 97 of 108 enhanced definition table 85. ed configuration scripts input format input data width 1 synchronization format input color space output color space table number 525p at 59.94 hz 10 - b it ddr eav/sav ycrcb yprpb table 86 525p at 59.94 hz 10-b it ddr hsync / vsync ycrcb yprpb table 87 525p at 59.94 hz 10-b it ddr eav/sav ycrcb rgb table 88 525p at 59.94 hz 10-b it ddr hsync / vsy nc ycrcb rgb table 89 525p at 59.94 hz 20-b it sdr eav/sav ycrcb yprpb table 90 525p at 59.94 hz 20-b it sdr hsync / vsync ycrcb yprpb table 91 525p at 59.94 hz 20-b it sdr eav/sav ycrcb rgb table 92 525p at 59.94 hz 20-b it sdr hsync / vsync ycrcb rgb table 93 525p at 59.94 hz 30-b it sdr eav/sav ycrcb yprpb table 94 525p at 59.94 hz 30-b it sdr hsync / vsync ycrcb yprpb table 95 525p at 59.94 hz 30 - b it sdr eav/sav ycrcb rgb table 96 525p at 59.94 hz 30-b it sdr hsync / vsync ycrcb rgb table 97 525p at 59.94 hz 30-b it sdr hsync / vsync rgb rgb table 98 625p at 50 hz 10-b it ddr eav/sav ycrcb yprpb table 99 625p at 50 hz 10-b it ddr hsync / vsync ycrcb yprpb table 100 625p at 50 hz 10-bi t ddr eav/sav ycrcb rgb table 101 625p at 50 hz 10-b it ddr hsync / vsync ycrcb rgb table 102 625p at 50 hz 20-b it sdr eav/sav ycrcb yprpb table 103 625p at 50 hz 20 - b it sdr hsync / vsync ycrcb yprpb table 104 625p at 50 hz 20-b it sdr eav/sav ycrcb rgb table 105 625p at 50 hz 20-b it sdr hsync / vsync ycrcb rgb table 106 625p at 50 hz 30-b it sdr eav/sav ycrcb yprpb table 107 625p at 50 hz 30-b it sdr hsync / vsync ycrcb yprpb table 108 625p at 50 hz 30 - b it sdr eav/sav ycrcb rgb table 109 625p at 50 hz 30-b it sdr hsync / vsync ycrcb rgb table 110 625p at 50 hz 30- bit sdr hsync / vsync rgb rgb table 111 1 sdr = single data rate. ddr = dual data rate. table 86. 10 - bit 525p ycrcb in (eav/sav), yprpb out subaddress setting description 0 x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed - ddr input mode. luma data clocked on falling edge of clkin. 0x30 0x04 525p at 59.94 hz. eav/sav synchro - nization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled. table 87. 10 - bit 525p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed - ddr input mode. luma data clocked o n falling edge of clkin. 0x30 0x00 525p at 59.94 hz. hsync / vsync synchro nization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled.
ADV7344 data sheet rev. b | page 98 of 108 table 88. 10 - bit 525p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed - ddr input mode. luma data clocked on falling edge of clkin. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x04 525p at 59.94 hz. eav/sav synchro - nization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled. table 89. 10 - bit 525p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed - ddr input mode. luma data clocked on falling edge of clkin. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x00 525p at 59.94 hz. hsy nc / vsync synchro nization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled. table 90. 20 - bit 525p ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0 x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x30 0x04 525p at 59.94 hz. eav/sav synchroni - zation. eia- 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 91. 20 - bit 525p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x30 0x00 525p at 59.94 hz. hsy nc / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 92. 20 - bit 525p ycrcb in (eav/sav), rgb out subaddress setting de scription 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x04 525p at 59.94 hz. eav/sav synchroni - zation. eia- 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 93. 20 - bit 525p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x00 525p at 59.94 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 94. 30 - bit 525p ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x30 0x04 525p at 59.94 hz. eav/sav synchroni - zation. eia- 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 95. 30 - bit 525p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x30 0x00 525p at 59.94 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixe l data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit).
data sheet ADV7344 rev. b | page 99 of 108 table 96. 30 - bit 525p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enable d (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x04 525p at 59.94 hz. eav/sav synchroni - zation. eia- 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 97. 30 - bit 525p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x00 525p at 59.94 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 98. 30 - bit 525p rgb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x00 525p at 59.94 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). 0x35 0x02 rgb input enabled . table 99. 10 - bit 625p ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed - ddr input mode. luma data clocked on falling edge of clkin. 0x30 0x1c 625p at 50 hz. eav/sav synchroniza - tion. eia- 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled. table 100. 10- bit 625p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software rese t. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed - ddr input mode. luma data clocked on falling edge of clkin. 0x30 0x18 625p at 50 hz. hsync / vsync synchronization. eia- 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled. table 101. 10- bit 625p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed -ddr input mode. luma data clocked on falling edge of clkin. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x1c 625p at 50 hz. eav/sav synchroni - zation. eia- 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10 - bit input enabled. tab le 102 . 10- bit 625p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x20 ed - ddr input mode. luma data clocked on falling edge of clkin. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x18 625p at 5 0 hz. hsync / vsync synchroni zation. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled. table 103. 20- bit 625p ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x30 0x1c 625p at 50 hz. eav/sav synchroni - zation. eia- 770.2 outpu t levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit).
ADV7344 data sheet rev. b | page 100 of 108 table 104. 20- bit 625p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enable d (8). 0x01 0x10 ed - sdr input mode. 0x30 0x18 625p at 5 0 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 105. 20- bit 625p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x1c 625p at 5 0 hz. eav/sav synch roniza - tion. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 106. 20- bit 625p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x18 625p at 5 0 hz. hsync / vsync synch - roniza tion. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x6c 10 - bit input enabled (10 2 = 20 - bit). table 107. 30- bit 625p ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x30 0x1c 625p at 5 0 hz. eav/sav synchroniza - tion. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 108. 30- bit 625p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x30 0x18 625p at 5 0 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 109. 30- bit 625p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x1c 625p at 5 0 hz. eav/sav synch roniza - tion. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 110. 30- bit 625p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabl ed (8). 0x01 0x10 ed - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x18 625p at 5 0 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 111. 30- bit 625p rgb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (8). 0x01 0x10 ed - sdr inpu t mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x18 625p at 5 0 hz. hsync / vsync synch - ronization. eia - 770.2 output levels. 0x31 0x01 pixel data valid. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). 0x35 0x02 rgb input enabled .
data sheet ADV7344 rev. b | page 101 of 108 high definition table 112. hd configuration scripts input format input data width 1 synchronization format input color space output color space table number 720p at 6 0 hz/59.94 hz 10 - b it ddr eav/sav ycrcb yprpb table 113 720p at 60 hz/59.94 hz 10-b it ddr hsync / vsync ycrcb yprpb table 114 720p at 60 hz/59.94 hz 10-b it dd r eav/sav ycrcb rgb table 115 720p at 60 hz/59.94 hz 10-b it ddr hsync / vsync ycrcb rgb table 116 720p at 60 hz/59.94 hz 20-b it sdr eav/sav ycrcb yprpb table 117 720p at 60 hz/59.94 hz 20-b it sdr hsync / vsync ycrcb yprpb table 118 720p at 60 hz/59.94 hz 20-b it sdr eav/sav ycrcb rgb table 119 720p at 60 hz/59.94 hz 20-b it sdr hsync / vsync ycrcb rgb table 120 720p at 60 hz/59.94 hz 30-b it sdr eav/sav ycrcb yprpb table 121 720p at 60 hz/59.94 hz 30-b it sdr hsync / vsync ycrcb yprpb table 122 720p at 60 hz/59.94 hz 30 - b it sdr eav/sav ycrcb rgb table 123 720p at 60 hz/59.94 hz 30-b it sdr hsync / vsync ycrcb rgb table 124 720p at 60 hz/59.94 hz 30-b it sdr hsync / vsync rgb rgb table 125 1080i at 30 hz /29.9 7 hz 10-b it ddr eav/sav ycrcb yprpb table 126 1080i at 30 hz /29.9 7 hz 10-b it ddr hsync / vsync ycrcb yprpb table 127 1080i at 30 hz /29.9 7 hz 10-b it ddr eav/sav ycrcb rgb table 128 1080i at 30 hz /29.9 7 hz 10-b it ddr hsync / vsync ycrcb rgb table 129 1080i at 30 hz /29.9 7 hz 20-b it sdr eav/sav ycrcb yprpb table 130 1080i at 30 hz /29.9 7 hz 20 - b it sdr hsync / vsync ycrcb yprpb table 131 1080i at 30 hz /29.9 7 hz 20-b it sdr eav/sav ycrcb rgb table 132 1080i at 30 hz /29.9 7 hz 20-b it sdr hsync / vsync ycrcb rgb table 133 1080i at 30 hz /29.9 7 hz 30-b it sdr eav/sav ycrcb yprpb table 134 1080i at 30 hz /29.9 7 hz 30-bi t sdr hsync / vsync ycrcb yprpb table 135 1080i at 30 hz /29.9 7 hz 30 - b it sdr eav/sav ycrcb rgb table 136 1080i at 30 hz /29.9 7 hz 30-b it sdr hsync / vsync ycrcb rgb table 137 1080i at 30 hz /29.9 7 hz 30-b it sdr hsync / vsync rgb rgb table 138 1 sdr = single data rate. ddr = dual data rate. table 113. 10- bit 720p ycrcb in (eav/sav) , yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x20 hd - ddr input mode. luma data clocked on falling edge of clkin. 0x30 0x2c 720p at 60 hz /59 .94 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled. table 114. 10- bit 720p ycrcb in, yprpb out subaddress setting description 0x17 0x02 softwa re reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x20 hd - ddr input mode. luma data clocked on falling edge of clkin. 0x30 0x28 720p at 60 hz /59.94 hz. hsync / vsync syn chronization. eia - 770.3 outp ut levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled.
ADV7344 data sheet rev. b | page 102 of 108 table 115. 10- bit 720p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pl l enabled (4). 0x01 0x20 hd - ddr input mode. luma data clocked on falling edge of clkin. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x2c 720p at 60 hz /59.94 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data va lid. 4 oversampling. 0x33 0x6c 10- bit input enabled. table 116. 10- bit 720p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x20 hd - ddr input mode. luma data clocked on falling edge of clkin. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x28 720p at 60 hz /59.94 hz. hsync / vsync syn chronization. eia - 770.3 output levels. 0x31 0x01 pixel da ta valid. 4 oversampling. 0x33 0x6c 10- bit input enabled. table 117. 20- bit 720p ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x30 0x2c 720p at 60 hz/59.94 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 118 . 20 - bit 720p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x30 0x28 720p at 60 hz /59.94 hz. hsync / vsync synchronizati on. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 119. 20- bit 720p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software r eset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x2c 720p at 60 hz/59.94 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 120 . 20 - bit 720p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd -sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x28 720p at 60 hz /59.94 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0 x6c 10- bit input enabled (10 2 = 20 - bit). table 121. 30- bit 720p ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode . 0x30 0x2c 720p at 60 hz/59.94 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 122 . 30 - bit 720p ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x30 0x28 720p at 60 hz /59.94 hz. hsync / vsync synchronizat ion. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit).
data sheet ADV7344 rev. b | page 103 of 108 table 123. 30- bit 720p ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x2c 720p at 60 hz/59.94 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 124 . 30 - bit 720p ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled . pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x28 720p at 60 hz /59.94 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixe l data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 125 . 30 - bit 720p rgb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x28 720p at 60 hz /59.94 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). 0x35 0x02 rgb input enabled . table 126. 10- bit 1080i ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software r eset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x20 hd - ddr input mode. luma data clocked on falling edge of clkin. 0x30 0x6c 1080i at 30 hz /29.9 7 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampli ng. 0x33 0x6c 10 - bit input enabled. table 127. 10- bit 1080i ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x20 hd - ddr input mode. luma data clo cked on falling edge of clkin. 0x30 0x68 1080i at 30 hz/29.97 hz. hsync / vsync syn chronization. eia-770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled. table 128. 10- bit 1080i ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x20 hd - ddr input mode. luma data clocked on falling edge of clkin. 0x02 0 x10 rgb output enabled. rgb output sync enabled. 0x30 0x6c 1080i at 30 hz/29.97 hz. hsync / vsync syn chronization. eia-770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled. table 129. 10- bit 1080i ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x20 hd - ddr input mode. luma data clocked on falling edge of clkin. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x68 1080i at 30 hz /29.9 7 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10 - bit input enabled. table 130. 20- bit 1080i ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x30 0x6c 1080i at 30 hz /29.9 7 hz. eav/sav syn - chronization. eia - 770.3 ou tput levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit).
ADV7344 data sheet rev. b | page 104 of 108 table 131 . 20 - bit 1080i ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dac s enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x30 0x68 1080i at 30 hz/29.97 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10-b it input enabled (10 2 = 20 - bit). table 132 . 20 - bit 1080i ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0 x10 rgb output enabled. rgb output sync enabled. 0x30 0x6c 1080i at 30 hz /29.9 7 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10- bit input enabled (10 2 = 20 - bit). table 133. 20- bit 1080i ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x68 1080i at 30 hz/29.97 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x6c 10 - bit input enabled (10 2 = 20 - bit). table 134. 30- bit 1080i ycrcb in (eav/sav), yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x30 0x6c 1080i at 30 hz /29.9 7 hz. eav/sav syn - chronization. eia - 770.3 output level s. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 135 . 30 - bit 1080i ycrcb in, yprpb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1 c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x30 0x68 1080i at 30 hz/29.97 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 136 . 30 - bit 1080i ycrcb in (eav/sav), rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x6c 1080i at 30 hz /29.9 7 hz. eav/sav syn - chronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabl ed (10 3 = 30 - bit). table 137. 30- bit 1080i ycrcb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x68 1080i at 30 hz/29.97 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). table 138. 30- bit 1080i rgb in, rgb out subaddress setting description 0x17 0x02 software reset. 0x00 0x1c all dacs enabled. pll enabled (4). 0x01 0x10 hd - sdr input mode. 0x02 0x10 rgb output enabled. rgb output sync enabled. 0x30 0x68 1080i at 30 hz/29.97 hz. hsync / vsync synchronization. eia - 770.3 output levels. 0x31 0x01 pixel data valid. 4 oversampling. 0x33 0x2c 4:4:4 input data. 10 - bit input enabled (10 3 = 30 - bit). 0x35 0x02 rgb input enabled .
data sheet ADV7344 rev. b | page 105 of 108 outline dimensions compliant t o jedec s t andards ms-026-bcd 051706- a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 138 . 64 - lead low profile quad flat package [lqfp] (st- 64- 2) dimensions shown in millimeters ordering guide model 1 temperature range macrovision 2 anti taping package description package option ad v7344bstz ?40 c to +85 c yes 64- lead low profile quad flat package [lqfp] st-64-2 eval -ADV7344ebz yes evaluation platform 1 z = rohs compliant part. 2 macrovision - enabled ics require the buyer to be an approved licensee (authorized buyer) of ics that are able to output macrovision rev 7.1.l1 - compliant video.
ADV7344 data sheet rev. b | page 106 of 108 notes
data sheet ADV7344 rev. b | page 107 of 108 notes
ADV7344 data sheet rev. b | page 108 of 10 8 notes purchase of licensed i 2 c components of anal og devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by ph ilips. ? 2006 - 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06400 -0- 2/12(b)

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